{"id":"https://openalex.org/W4416799397","doi":"https://doi.org/10.1109/icriset64803.2025.11251606","title":"Implementation of Sorting Algorithms Using FPGA","display_name":"Implementation of Sorting Algorithms Using FPGA","publication_year":2025,"publication_date":"2025-08-01","ids":{"openalex":"https://openalex.org/W4416799397","doi":"https://doi.org/10.1109/icriset64803.2025.11251606"},"language":"en","primary_location":{"id":"doi:10.1109/icriset64803.2025.11251606","doi":"https://doi.org/10.1109/icriset64803.2025.11251606","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icriset64803.2025.11251606","pdf_url":null,"source":{"id":"https://openalex.org/S7407096217","display_name":"International Conference on Recent Innovation in Science Engineering and Technology (ICRISET)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 International Conference on Recent Innovation in Science Engineering and Technology (ICRISET)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084105687","display_name":"P. Anuradha","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I134892692","display_name":"Chaitanya Bharathi Institute of Technology","ror":"https://ror.org/047ymzq84","country_code":"IN","type":"education","lineage":["https://openalex.org/I134892692"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P Anuradha","raw_affiliation_strings":["Chaitanya Bharathi Institute of Technology,Department of ECE,Hyderabad,Telangana"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chaitanya Bharathi Institute of Technology,Department of ECE,Hyderabad,Telangana","institution_ids":["https://openalex.org/I134892692"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040937883","display_name":"Golla Bala Renuka","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"G Renuka","raw_affiliation_strings":["Anurag University,Department of ECE,Hyderabad,Telangana"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Anurag University,Department of ECE,Hyderabad,Telangana","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5092956806","display_name":"V. Gurumurthy","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"V.Gurumurthy","raw_affiliation_strings":["Anurag University,Department of ECE,Hyderabad,Telangana"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Anurag University,Department of ECE,Hyderabad,Telangana","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101955312","display_name":"K. Rajkumar","orcid":"https://orcid.org/0000-0002-3592-6546","observed_orcids":["https://orcid.org/0000-0002-3592-6546"]},"institutions":[{"id":"https://openalex.org/I4405263155","display_name":"SR University","ror":"https://ror.org/039t32v17","country_code":"IN","type":"education","lineage":["https://openalex.org/I4405263155"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K Rajkumar","raw_affiliation_strings":["SR University,Department of ECE,Warangal,Telangana"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"SR University,Department of ECE,Warangal,Telangana","institution_ids":["https://openalex.org/I4405263155"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5092731212","display_name":"Ch. Navitha","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I134892692","display_name":"Chaitanya Bharathi Institute of Technology","ror":"https://ror.org/047ymzq84","country_code":"IN","type":"education","lineage":["https://openalex.org/I134892692"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ch. Navitha","raw_affiliation_strings":["Chaitanya Bharathi Institute of Technology,Department of ECE,Hyderabad,Telangana"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chaitanya Bharathi Institute of Technology,Department of ECE,Hyderabad,Telangana","institution_ids":["https://openalex.org/I134892692"]}]},{"author_position":"last","author":{"id":null,"display_name":"Degam Sai Krishna","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I134892692","display_name":"Chaitanya Bharathi Institute of Technology","ror":"https://ror.org/047ymzq84","country_code":"IN","type":"education","lineage":["https://openalex.org/I134892692"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Degam Sai Krishna","raw_affiliation_strings":["Chaitanya Bharathi Institute of Technology,Department of ECE,Hyderabad,Telangana"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Chaitanya Bharathi Institute of Technology,Department of ECE,Hyderabad,Telangana","institution_ids":["https://openalex.org/I134892692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4541,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54065198,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.673799991607666,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.673799991607666,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.30320000648498535,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.011599999852478504,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.6579999923706055},{"id":"https://openalex.org/keywords/sorting-algorithms","display_name":"sorting algorithms","score":0.9110000133514404},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"parallel computing","score":0.5870000123977661},{"id":"https://openalex.org/keywords/bubble-sort","display_name":"bubble sort","score":0.9789999723434448},{"id":"https://openalex.org/keywords/selection-sort","display_name":"selection sort","score":0.996999979019165},{"id":"https://openalex.org/keywords/insertion-sort","display_name":"insertion sort","score":1.0},{"id":"https://openalex.org/keywords/hardware-software-co-design","display_name":"hardware-software co-design","score":0.9100000262260437},{"id":"https://openalex.org/keywords/fpga-resource-usage","display_name":"FPGA resource usage","score":0.6819999814033508},{"id":"https://openalex.org/keywords/execution-time-comparison","display_name":"execution time comparison","score":0.5730000138282776},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"hardware acceleration","score":0.4790000021457672}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8278999924659729},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8112000226974487},{"id":"https://openalex.org/C111696304","wikidata":"https://www.wikidata.org/wiki/Q2303697","display_name":"Sorting","level":2,"score":0.800599992275238},{"id":"https://openalex.org/C108094655","wikidata":"https://www.wikidata.org/wiki/Q181593","display_name":"Sorting algorithm","level":3,"score":0.7597000002861023},{"id":"https://openalex.org/C88548561","wikidata":"https://www.wikidata.org/wiki/Q347599","display_name":"sort","level":2,"score":0.5356000065803528},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5059000253677368},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40130001306533813},{"id":"https://openalex.org/C206345919","wikidata":"https://www.wikidata.org/wiki/Q20380951","display_name":"Resource (disambiguation)","level":2,"score":0.3801000118255615},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3781000077724457},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.3603000044822693},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34150001406669617},{"id":"https://openalex.org/C64540648","wikidata":"https://www.wikidata.org/wiki/Q646477","display_name":"Sorting network","level":4,"score":0.3409000039100647},{"id":"https://openalex.org/C81917197","wikidata":"https://www.wikidata.org/wiki/Q628760","display_name":"Selection (genetic algorithm)","level":2,"score":0.33820000290870667},{"id":"https://openalex.org/C106516650","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm design","level":2,"score":0.3165000081062317},{"id":"https://openalex.org/C106515295","wikidata":"https://www.wikidata.org/wiki/Q26806595","display_name":"Parallel processing","level":2,"score":0.3052000105381012},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.27570000290870667},{"id":"https://openalex.org/C138827492","wikidata":"https://www.wikidata.org/wiki/Q6661985","display_name":"Data processing","level":2,"score":0.2567000091075897},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2500999867916107}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icriset64803.2025.11251606","doi":"https://doi.org/10.1109/icriset64803.2025.11251606","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icriset64803.2025.11251606","pdf_url":null,"source":{"id":"https://openalex.org/S7407096217","display_name":"International Conference on Recent Innovation in Science Engineering and Technology (ICRISET)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 International Conference on Recent Innovation in Science Engineering and Technology (ICRISET)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2598473217","https://openalex.org/W3012502592","https://openalex.org/W3111247291","https://openalex.org/W3144691359","https://openalex.org/W4210494990","https://openalex.org/W4366151863","https://openalex.org/W4387068377","https://openalex.org/W4387101124","https://openalex.org/W4407467934","https://openalex.org/W4409254355","https://openalex.org/W4409763592"],"related_works":["https://openalex.org/W7152037820","https://openalex.org/W2598473217","https://openalex.org/W4407910223","https://openalex.org/W2940446214","https://openalex.org/W3012502592","https://openalex.org/W6887472260","https://openalex.org/W2808534810","https://openalex.org/W4210298350","https://openalex.org/W4285317294","https://openalex.org/W102794282"],"abstract_inverted_index":{"This":[0,151],"study":[1,104],"proposes":[2],"an":[3,110],"FPGA-based":[4],"method":[5],"for":[6],"improving":[7],"the":[8,89,142],"performance":[9],"of":[10,27,53,105,118,129,144],"traditional":[11,40],"sorting":[12,33,42,107],"algorithms":[13,87,108],"by":[14,48,165],"utilizing":[15],"Field-Programmable":[16],"Gate":[17],"Arrays'":[18],"(FPGAs')":[19],"parallel":[20],"processing":[21,160],"capabilities.":[22],"Our":[23],"strategy":[24],"takes":[25],"advantage":[26],"hardware-level":[28],"parallelism":[29],"to":[30,39,76,82,146,155],"greatly":[31],"increase":[32],"speed":[34,147],"and":[35,58,84,94,123,157],"efficiency,":[36],"in":[37,66,88,109,116,161],"contrast":[38],"software-based":[41],"techniques":[43,74],"that":[44],"are":[45],"frequently":[46],"constrained":[47],"sequential":[49],"execution.":[50],"The":[51,102],"implementation":[52,96],"Bubble":[54],"Sort,":[55,57],"Selection":[56],"Insertion":[59],"Sort":[60],"on":[61,97],"FPGA":[62,98,111,145],"hardware":[63],"is":[64,80,125],"examined":[65],"this":[67,130],"work,":[68],"which":[69],"also":[70],"introduces":[71],"novel":[72],"parallelization":[73],"specific":[75],"each":[77],"algorithm,":[78],"Vivado":[79],"used":[81],"create":[83],"describe":[85],"these":[86],"proposed":[90],"system.":[91],"Simulation,":[92],"synthesis,":[93],"practical":[95],"development":[99],"board":[100],"follows.":[101],"comparative":[103],"several":[106],"context,":[112],"assessing":[113],"their":[114],"trade-offs":[115],"terms":[117],"execution":[119],"time,":[120],"resource":[121],"usage,":[122],"scalability,":[124],"a":[126],"significant":[127,135],"innovation":[128],"work.":[131],"Performance":[132],"analysis":[133],"shows":[134],"gains":[136],"over":[137],"conventional":[138],"CPU-based":[139],"sorting,":[140],"indicating":[141],"potential":[143],"up":[148],"computational":[149],"operations.":[150],"discovery":[152],"has":[153],"contributed":[154],"efficient":[156],"high-performance":[158],"data":[159],"modern":[162],"computer":[163],"systems":[164],"providing":[166],"insights":[167],"into":[168],"hardware-software":[169],"co-design.":[170]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-11-12T12:28:57.059296","created_date":"2025-11-28T00:00:00"}