{"id":"https://openalex.org/W4416728107","doi":"https://doi.org/10.1109/mwscas53549.2025.11244518","title":"Parameterized Low-Overhead Data Conversion Architectures for Posit Arithmetic","display_name":"Parameterized Low-Overhead Data Conversion Architectures for Posit Arithmetic","publication_year":2025,"publication_date":"2025-08-10","ids":{"openalex":"https://openalex.org/W4416728107","doi":"https://doi.org/10.1109/mwscas53549.2025.11244518"},"language":null,"primary_location":{"id":"doi:10.1109/mwscas53549.2025.11244518","doi":"https://doi.org/10.1109/mwscas53549.2025.11244518","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas53549.2025.11244518","pdf_url":null,"source":{"id":"https://openalex.org/S4210192229","display_name":"Conference proceedings","issn_l":"1548-3746","issn":["1548-3746","1558-3899"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Diksha Shekhawat","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Diksha Shekhawat","raw_affiliation_strings":["CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120477412","display_name":"Manashvi Pangoria","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Manashvi Pangoria","raw_affiliation_strings":["Birla Institute of Technology and Science (BITS),Pilani,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology and Science (BITS),Pilani,India","institution_ids":["https://openalex.org/I74796645"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108262556","display_name":"V. Sreejith","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vaishak Sreejith","raw_affiliation_strings":["Birla Institute of Technology and Science (BITS),Pilani,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology and Science (BITS),Pilani,India","institution_ids":["https://openalex.org/I74796645"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087628279","display_name":"Jugal Gandhi","orcid":"https://orcid.org/0000-0001-8720-1582","observed_orcids":["https://orcid.org/0000-0001-8720-1582"]},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jugal Gandhi","raw_affiliation_strings":["CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011088447","display_name":"Jai Gopal Pandey","orcid":"https://orcid.org/0000-0001-9937-7438","observed_orcids":["https://orcid.org/0000-0001-9937-7438"]},"institutions":[{"id":"https://openalex.org/I41763900","display_name":"Central Electronics Engineering Research Institute","ror":"https://ror.org/01hh45364","country_code":"IN","type":"facility","lineage":["https://openalex.org/I2799351866","https://openalex.org/I41763900","https://openalex.org/I4210134808","https://openalex.org/I66760702"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jai Gopal Pandey","raw_affiliation_strings":["CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CSIR- Central Electronics Engineering Research Institute (CEERI),Pilani,India,333031","institution_ids":["https://openalex.org/I41763900"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100712113","display_name":"Chandra Shekhar","orcid":"https://orcid.org/0000-0002-2114-9096","observed_orcids":["https://orcid.org/0000-0002-2114-9096","https://orcid.org/0000-0003-2818-5361","https://orcid.org/0000-0002-5046-4888"]},"institutions":[{"id":"https://openalex.org/I74796645","display_name":"Birla Institute of Technology and Science, Pilani","ror":"https://ror.org/001p3jz28","country_code":"IN","type":"education","lineage":["https://openalex.org/I74796645"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Chandra Shekhar","raw_affiliation_strings":["Birla Institute of Technology and Science (BITS),Pilani,India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Birla Institute of Technology and Science (BITS),Pilani,India","institution_ids":["https://openalex.org/I74796645"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.43017072,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"69","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.00419999985024333,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.6909999847412109}],"concepts":[{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.8375999927520752},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.7196000218391418},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6883000135421753},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6626999974250793},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.578499972820282},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5784000158309937},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47380000352859497},{"id":"https://openalex.org/C1232282","wikidata":"https://www.wikidata.org/wiki/Q1783551","display_name":"Data conversion","level":2,"score":0.4368000030517578},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.41110000014305115},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4059000015258789},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.3944000005722046},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.35910001397132874},{"id":"https://openalex.org/C2780388253","wikidata":"https://www.wikidata.org/wiki/Q5421508","display_name":"Exponent","level":2,"score":0.35740000009536743},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3472000062465668},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34610000252723694},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34549999237060547},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.31850001215934753},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.29809999465942383},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2976999878883362},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.2928999960422516},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2906000018119812},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.289900004863739},{"id":"https://openalex.org/C204241405","wikidata":"https://www.wikidata.org/wiki/Q461499","display_name":"Transformation (genetics)","level":3,"score":0.28780001401901245},{"id":"https://openalex.org/C90673727","wikidata":"https://www.wikidata.org/wiki/Q901718","display_name":"Product (mathematics)","level":2,"score":0.2858000099658966},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.2777000069618225},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.259799987077713},{"id":"https://openalex.org/C118993495","wikidata":"https://www.wikidata.org/wiki/Q5042828","display_name":"Electrical efficiency","level":3,"score":0.2590999901294708}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas53549.2025.11244518","doi":"https://doi.org/10.1109/mwscas53549.2025.11244518","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas53549.2025.11244518","pdf_url":null,"source":{"id":"https://openalex.org/S4210192229","display_name":"Conference proceedings","issn_l":"1548-3746","issn":["1548-3746","1558-3899"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W2743322459","https://openalex.org/W2799131675","https://openalex.org/W2802631930","https://openalex.org/W3152828401","https://openalex.org/W3185437734","https://openalex.org/W3211586661","https://openalex.org/W4286656557","https://openalex.org/W4312632053","https://openalex.org/W4312744061","https://openalex.org/W4312910656","https://openalex.org/W4376473371","https://openalex.org/W4385489572","https://openalex.org/W4388483476","https://openalex.org/W4391215994","https://openalex.org/W4392907995","https://openalex.org/W4394629071","https://openalex.org/W4399239357","https://openalex.org/W4407169371","https://openalex.org/W4409568286"],"related_works":[],"abstract_inverted_index":{"Posit":[0],"has":[1],"emerged":[2],"as":[3],"a":[4],"dynamic":[5],"floating-point":[6],"representation":[7],"that":[8],"adapts":[9],"its":[10],"fractional":[11],"size":[12],"based":[13],"on":[14,92,112],"the":[15,20,78,113,121,125,130,147],"numerical":[16],"requirements,":[17],"enabled":[18],"by":[19],"additional":[21],"regime":[22,46],"field.":[23],"A":[24],"posit":[25,41,126],"conversion":[26,42],"unit":[27],"ensures":[28],"efficient":[29],"format":[30],"adaptation":[31],"for":[32,40,62],"hardware":[33,56,154],"processing.":[34],"This":[35],"paper":[36],"proposes":[37],"parameterized":[38,149],"architectures":[39,59,71,123],"units":[43],"with":[44,50,124,159],"optimized":[45],"and":[47,54,65,88,115,156],"exponent":[48],"computation":[49],"improved":[51,153],"datapath":[52],"efficiency":[53],"reduced":[55],"overhead.":[57],"The":[58,95,144],"are":[60],"validated":[61],"16,":[63],"32,":[64],"64-bit":[66],"posits.":[67],"Compared":[68],"to":[69],"existing":[70],"in":[72,86,90,104,107],"terms":[73],"of":[74,84,102],"power-performance-area":[75],"(PPA)":[76],"overhead,":[77],"proposed":[79,122,148],"work":[80],"shows":[81,99],"an":[82,100],"improvement":[83,101],"2-18%":[85],"resources":[87],"6-37%":[89],"performance":[91],"FPGA":[93],"devices.":[94],"post-synthesis":[96],"PPA":[97],"evaluation":[98],"10-66%":[103],"area,":[105],"34-72%":[106],"delay,":[108],"and$35-78":[109],"\\%$in":[110],"power":[111],"28":[114],"45":[116,139],"nm":[117],"technology":[118],"nodes.":[119],"Integrating":[120],"adder/multiplier":[127],"modules":[128],"improves":[129],"average":[131],"area-power-delay":[132],"product":[133],"by$62.74":[134],"/":[135,138],"35.83":[136],"\\%$on$28":[137],"~\\text{nm}$technology":[140],"over":[141],"state-of-the-art":[142],"designs.":[143],"results":[145],"validate":[146],"architectures,":[150],"demonstrating":[151],"low-overhead,":[152],"efficiency,":[155],"scalable":[157],"integration":[158],"arithmetic":[160],"modules.":[161]},"counts_by_year":[],"updated_date":"2026-10-06T10:28:23.643775","created_date":"2025-11-25T00:00:00"}
