{"id":"https://openalex.org/W4406138916","doi":"https://doi.org/10.1109/piere62470.2024.10805030","title":"A Set-Based Theoretical Model of IP-Cores for IC Design on Reconfigurable SoC","display_name":"A Set-Based Theoretical Model of IP-Cores for IC Design on Reconfigurable SoC","publication_year":2024,"publication_date":"2024-11-15","ids":{"openalex":"https://openalex.org/W4406138916","doi":"https://doi.org/10.1109/piere62470.2024.10805030"},"language":"en","primary_location":{"id":"doi:10.1109/piere62470.2024.10805030","doi":"https://doi.org/10.1109/piere62470.2024.10805030","is_oa":false,"landing_page_url":"https://doi.org/10.1109/piere62470.2024.10805030","pdf_url":null,"source":{"id":"https://openalex.org/S7407096329","display_name":"IEEE International Conference on Problems of Informatics, Electronics and Radio Engineering (PIERE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 3rd International Conference on Problems of Informatics, Electronics and Radio Engineering (PIERE)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053906683","display_name":"S. V. Gavrilov","orcid":"https://orcid.org/0000-0003-0566-4482","observed_orcids":["https://orcid.org/0000-0003-0566-4482"]},"institutions":[{"id":"https://openalex.org/I2800235667","display_name":"Kurchatov Institute","ror":"https://ror.org/00n1nz186","country_code":"RU","type":"facility","lineage":["https://openalex.org/I2800235667"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Sergey V. Gavrilov","raw_affiliation_strings":["DDPM, CC NBICST, NRC &#x201C;Kurchatov Institute&#x201D;,CAD dept,Zelenograd,Russia"],"raw_orcid":"https://orcid.org/0000-0003-0566-4482","affiliations":[{"raw_affiliation_string":"DDPM, CC NBICST, NRC &#x201C;Kurchatov Institute&#x201D;,CAD dept,Zelenograd,Russia","institution_ids":["https://openalex.org/I2800235667"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013950156","display_name":"Daniil A. Zheleznikov","orcid":"https://orcid.org/0000-0003-2477-1793","observed_orcids":["https://orcid.org/0000-0003-2477-1793"]},"institutions":[{"id":"https://openalex.org/I2800235667","display_name":"Kurchatov Institute","ror":"https://ror.org/00n1nz186","country_code":"RU","type":"facility","lineage":["https://openalex.org/I2800235667"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Daniil A. Zheleznikov","raw_affiliation_strings":["DDPM, CC NBICST, NRC &#x201C;Kurchatov Institute&#x201D;,CAD dept,Zelenograd,Russia"],"raw_orcid":"https://orcid.org/0000-0003-2477-1793","affiliations":[{"raw_affiliation_string":"DDPM, CC NBICST, NRC &#x201C;Kurchatov Institute&#x201D;,CAD dept,Zelenograd,Russia","institution_ids":["https://openalex.org/I2800235667"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025699661","display_name":"Mariya A. Zapletina","orcid":"https://orcid.org/0000-0001-9845-7823","observed_orcids":["https://orcid.org/0000-0001-9845-7823"]},"institutions":[{"id":"https://openalex.org/I2800235667","display_name":"Kurchatov Institute","ror":"https://ror.org/00n1nz186","country_code":"RU","type":"facility","lineage":["https://openalex.org/I2800235667"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Maria A. Zapletina","raw_affiliation_strings":["DDPM, CC NBICST, NRC &#x201C;Kurchatov Institute&#x201D;,CAD dept,Zelenograd,Russia"],"raw_orcid":"https://orcid.org/0000-0001-9845-7823","affiliations":[{"raw_affiliation_string":"DDPM, CC NBICST, NRC &#x201C;Kurchatov Institute&#x201D;,CAD dept,Zelenograd,Russia","institution_ids":["https://openalex.org/I2800235667"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082049065","display_name":"Vasilii M. Khvatov","orcid":"https://orcid.org/0000-0003-2285-4341","observed_orcids":["https://orcid.org/0000-0003-2285-4341"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vasilii M. Khvatov","raw_affiliation_strings":["IDPM RAS,CAD dept.,Zelenograd,Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IDPM RAS,CAD dept.,Zelenograd,Russia","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2322,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.4859662,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1170","last_page":"1174"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9814000129699707,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9814000129699707,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.016499999910593033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.000699999975040555,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ip-core","display_name":"IP core","score":0.8450000286102295},{"id":"https://openalex.org/keywords/soft-ip-core","display_name":"soft IP cores","score":0.8289999961853027},{"id":"https://openalex.org/keywords/placement","display_name":"placement","score":0.5059999823570251},{"id":"https://openalex.org/keywords/routing-resources","display_name":"routing resources","score":0.746999979019165},{"id":"https://openalex.org/keywords/computer-aided-design","display_name":"computer-aided design","score":0.8550000190734863}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6215603947639465},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5999702215194702},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5165833234786987},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5041118860244751},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4526668190956116},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4229128360748291},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16993305087089539}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/piere62470.2024.10805030","doi":"https://doi.org/10.1109/piere62470.2024.10805030","is_oa":false,"landing_page_url":"https://doi.org/10.1109/piere62470.2024.10805030","pdf_url":null,"source":{"id":"https://openalex.org/S7407096329","display_name":"IEEE International Conference on Problems of Informatics, Electronics and Radio Engineering (PIERE)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 3rd International Conference on Problems of Informatics, Electronics and Radio Engineering (PIERE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.428600013256073,"id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320327961","display_name":"National Research Center \"Kurchatov Institute\"","ror":"https://ror.org/037styt87"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1757537413","https://openalex.org/W2070608594","https://openalex.org/W2100580949","https://openalex.org/W2109656299","https://openalex.org/W2220804834","https://openalex.org/W2546035890","https://openalex.org/W4206246999","https://openalex.org/W4224288761","https://openalex.org/W4403278520"],"related_works":["https://openalex.org/W2160614746","https://openalex.org/W1492385613","https://openalex.org/W2018804200","https://openalex.org/W2099768573","https://openalex.org/W7097358835","https://openalex.org/W2114203340","https://openalex.org/W2028583644","https://openalex.org/W2030903985","https://openalex.org/W1995310333","https://openalex.org/W2120556855"],"abstract_inverted_index":{"The":[0,19,67],"paper":[1],"proposes":[2],"a":[3,11,15,60,65,80,95,122,160,165,176],"software-oriented":[4],"general":[5],"theoretical":[6],"model":[7,20,68,174],"of":[8,32,50,75,98,129,138,144,159,182],"IP-cores":[9,140],"in":[10,38,109,118,169],"reconfigurable":[12,62,77,119,145,162],"system":[13,63,78,163],"on":[14,64,79,121,164],"chip":[16,166],"design":[17,36,40],"flow.":[18],"represents":[21,69],"both":[22],"hard":[23,56],"and":[24,84,92,167,186],"soft":[25,47,139],"IP-":[26],"cores":[27,49,58],"uniformly":[28],"across":[29],"different":[30],"stages":[31],"the":[33,51,70,76,110,133,135,142,150,170,173,180],"integrated":[34,53,130],"circuit":[35,54],"flow":[37],"computer-aided":[39],"systems.":[41],"It":[42,89],"effectively":[43],"maps":[44],"architecturally":[45],"independent":[46,83],"IP":[48,57],"designed":[52,71,171],"into":[55],"from":[59],"targeted":[61],"chip.":[66],"circuit,":[72,172],"various":[73],"components":[74],"chip,":[81,123],"architecture":[82,85],"based":[86],"parameterized":[87],"IP-cores.":[88],"is":[90],"flexible":[91],"suitable":[93],"for":[94,101,155],"wide":[96],"range":[97],"modern":[99],"tools":[100],"VLSI":[102],"logic":[103],"synthesis.":[104],"Its":[105],"main":[106],"advantage":[107],"lies":[108],"ability":[111],"to":[112,125],"easily":[113],"incorporate":[114],"new":[115],"architectural":[116,147],"solutions":[117],"systems":[120],"leading":[124],"highly":[126],"effective":[127],"designs":[128],"circuits.":[131],"Within":[132],"model,":[134],"relative":[136],"coordinates":[137],"enable":[141],"exploitation":[143],"SoC":[146],"features":[148],"at":[149],"placement":[151],"stage.":[152],"By":[153],"accounting":[154],"specialized":[156],"routing":[157],"resources":[158],"basic":[161],"interconnections":[168],"achieves":[175],"good":[177],"trade-off":[178],"between":[179],"complexity":[181],"its":[183,187],"software":[184],"implementation":[185],"descriptive":[188],"capabilities.":[189]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2025-01-08T00:00:00"}
