{"id":"https://openalex.org/W4404157475","doi":"https://doi.org/10.1080/21681724.2024.2421114","title":"Design and analysis of 1-bit hybrid full adder cells for fast computation","display_name":"Design and analysis of 1-bit hybrid full adder cells for fast computation","publication_year":2024,"publication_date":"2024-11-06","ids":{"openalex":"https://openalex.org/W4404157475","doi":"https://doi.org/10.1080/21681724.2024.2421114"},"language":"en","primary_location":{"id":"doi:10.1080/21681724.2024.2421114","doi":"https://doi.org/10.1080/21681724.2024.2421114","is_oa":false,"landing_page_url":"https://doi.org/10.1080/21681724.2024.2421114","pdf_url":null,"source":{"id":"https://openalex.org/S2764407223","display_name":"International Journal of Electronics Letters","issn_l":"2168-1724","issn":["2168-1724","2168-1732"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1","poland-20","russia-white-list-2"],"host_organization":"https://openalex.org/P4310320547","host_organization_name":"Taylor & Francis","host_organization_lineage":["https://openalex.org/P4310320547","https://openalex.org/P4310320449"],"host_organization_lineage_names":["Taylor & Francis","Informa"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Electronics Letters","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114064523","display_name":"Anubhav Anand","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I144614875","display_name":"Alliance University","ror":"https://ror.org/03f4gsr42","country_code":"IN","type":"education","lineage":["https://openalex.org/I144614875"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Anubhav Anand","raw_affiliation_strings":["ACED, Alliance University","ACED, Alliance University, Bengaluru, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ACED, Alliance University","institution_ids":["https://openalex.org/I144614875"]},{"raw_affiliation_string":"ACED, Alliance University, Bengaluru, India","institution_ids":["https://openalex.org/I144614875"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Sandeep Dhariwal","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I144614875","display_name":"Alliance University","ror":"https://ror.org/03f4gsr42","country_code":"IN","type":"education","lineage":["https://openalex.org/I144614875"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sandeep Dhariwal","raw_affiliation_strings":["ACED, Alliance University","ACED, Alliance University, Bengaluru, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ACED, Alliance University","institution_ids":["https://openalex.org/I144614875"]},{"raw_affiliation_string":"ACED, Alliance University, Bengaluru, India","institution_ids":["https://openalex.org/I144614875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024643331","display_name":"Vijay Kumar Lamba","orcid":"https://orcid.org/0000-0003-2893-9514","observed_orcids":["https://orcid.org/0000-0003-2893-9514"]},"institutions":[{"id":"https://openalex.org/I244572783","display_name":"Symbiosis International University","ror":"https://ror.org/005r2ww51","country_code":"IN","type":"education","lineage":["https://openalex.org/I244572783"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Vijay Kumar Lamba","raw_affiliation_strings":["Symbiosis International University","Department of Electronics & Tele Communication, Symbiosis Institute of Technology-Pune, Symbiosis International University, Pune, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Symbiosis International University","institution_ids":["https://openalex.org/I244572783"]},{"raw_affiliation_string":"Department of Electronics & Tele Communication, Symbiosis Institute of Technology-Pune, Symbiosis International University, Pune, India","institution_ids":["https://openalex.org/I244572783"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5006967357","display_name":"Sankit Ramkrishna Kassa","orcid":"https://orcid.org/0000-0002-8714-2073","observed_orcids":["https://orcid.org/0000-0002-8714-2073"]},"institutions":[{"id":"https://openalex.org/I244572783","display_name":"Symbiosis International University","ror":"https://ror.org/005r2ww51","country_code":"IN","type":"education","lineage":["https://openalex.org/I244572783"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sankit Kassa","raw_affiliation_strings":["Symbiosis International University","Department of Electronics & Tele Communication, Symbiosis Institute of Technology-Pune, Symbiosis International University, Pune, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Symbiosis International University","institution_ids":["https://openalex.org/I244572783"]},{"raw_affiliation_string":"Department of Electronics & Tele Communication, Symbiosis Institute of Technology-Pune, Symbiosis International University, Pune, India","institution_ids":["https://openalex.org/I244572783"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5024643331"],"corresponding_institution_ids":["https://openalex.org/I244572783"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"13","issue":"1","first_page":"96","last_page":"107"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/full-adder","display_name":"full adder","score":0.8519999980926514},{"id":"https://openalex.org/keywords/gate-diffusion-input-logic","display_name":"gate diffusion input logic","score":0.7919999957084656},{"id":"https://openalex.org/keywords/transmission-gate-logic","display_name":"transmission gate logic","score":0.9079999923706055},{"id":"https://openalex.org/keywords/45-nm-cmos","display_name":"45 nm CMOS","score":0.8059999942779541},{"id":"https://openalex.org/keywords/low-power-digital-circuits","display_name":"low-power digital circuits","score":0.5099999904632568},{"id":"https://openalex.org/keywords/power-delay-product","display_name":"power-delay product","score":0.7670000195503235},{"id":"https://openalex.org/keywords/carry-generation","display_name":"carry generation","score":0.5289999842643738},{"id":"https://openalex.org/keywords/multiplexer","display_name":"multiplexer","score":0.8740000128746033}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.676461935043335},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.597931444644928},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5686464905738831},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.545033872127533},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.467457115650177},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4243733286857605},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.405063271522522},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.22566330432891846},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21284925937652588},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.18946895003318787},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18327763676643372},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.1328197419643402},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08868327736854553}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1080/21681724.2024.2421114","doi":"https://doi.org/10.1080/21681724.2024.2421114","is_oa":false,"landing_page_url":"https://doi.org/10.1080/21681724.2024.2421114","pdf_url":null,"source":{"id":"https://openalex.org/S2764407223","display_name":"International Journal of Electronics Letters","issn_l":"2168-1724","issn":["2168-1724","2168-1732"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","norway-1","poland-20","russia-white-list-2"],"host_organization":"https://openalex.org/P4310320547","host_organization_name":"Taylor & Francis","host_organization_lineage":["https://openalex.org/P4310320547","https://openalex.org/P4310320449"],"host_organization_lineage_names":["Taylor & Francis","Informa"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Electronics Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.5378999710083008,"display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W2076941448","https://openalex.org/W2124278579","https://openalex.org/W2131107384","https://openalex.org/W2138968074","https://openalex.org/W2141849037","https://openalex.org/W2208031660","https://openalex.org/W2910594020","https://openalex.org/W2972696482","https://openalex.org/W3016940091","https://openalex.org/W3034899143","https://openalex.org/W3162163331","https://openalex.org/W3163556913","https://openalex.org/W3194437664","https://openalex.org/W4224674582","https://openalex.org/W4283023098","https://openalex.org/W4323045097","https://openalex.org/W4386068073","https://openalex.org/W4386269521","https://openalex.org/W4388105024","https://openalex.org/W4389665034"],"related_works":["https://openalex.org/W4399300340","https://openalex.org/W3034899143","https://openalex.org/W2998002330","https://openalex.org/W7099400882","https://openalex.org/W4297896700","https://openalex.org/W4409517197","https://openalex.org/W2064699777","https://openalex.org/W2899979858","https://openalex.org/W3197055456","https://openalex.org/W2798410114"],"abstract_inverted_index":{"This":[0],"research":[1],"article":[2],"introduces":[3],"a":[4,39,42],"1-bit":[5],"Full":[6],"Adder":[7],"(FA)":[8],"cell":[9,24],"comprising":[10],"20":[11],"transistors,":[12],"employing":[13],"Gate":[14],"Diffusion":[15],"Input":[16],"(GDI)":[17],"and":[18,81,109],"transmission":[19,47],"gate":[20],"logic.":[21],"The":[22,53],"FA":[23],"is":[25,70,96],"segmented":[26],"into":[27],"four":[28],"modules:":[29],"the":[30,67,73,89,92],"first":[31],"module":[32,40],"encompasses":[33],"an":[34],"AND-OR":[35],"module,":[36],"followed":[37],"by":[38],"housing":[41],"Multiplexer":[43],"(MUX)":[44],"based":[45],"on":[46,72],"gates":[48,59],"for":[49],"Carry":[50],"Output":[51,63],"generation.":[52,64],"remaining":[54],"two":[55],"modules":[56],"are":[57],"XOR":[58],"dedicated":[60],"to":[61],"Sum":[62],"Simulation":[65],"of":[66,91],"proposed":[68,93],"design":[69],"conducted":[71],"45":[74,84],"nm":[75,85],"technology":[76],"node":[77],"using":[78],"Cadence":[79],"Virtuoso":[80],"its":[82],"GPDK":[83],"library.":[86],"To":[87],"validate":[88],"performance":[90,116],"design,":[94],"it":[95],"compared":[97],"against":[98],"existing":[99],"full":[100],"adders.":[101],"Performance":[102],"parameters":[103],"such":[104],"as":[105],"power":[106],"consumption,":[107],"delay":[108],"Power":[110],"Delay":[111],"Product":[112],"(PDP)":[113],"demonstrate":[114],"superior":[115],"across":[117],"voltages":[118],"ranging":[119],"from":[120],"0.8":[121],"V\u20131.2":[122],"V.":[123]},"counts_by_year":[],"updated_date":"2026-11-10T11:39:43.021295","created_date":"2024-11-08T00:00:00"}