{"id":"https://openalex.org/W4404133772","doi":"https://doi.org/10.1145/3649329.3657338","title":"Data-Efficient Conformalized Interval Prediction of Minimum Operating Voltage Capturing Process Variations","display_name":"Data-Efficient Conformalized Interval Prediction of Minimum Operating Voltage Capturing Process Variations","publication_year":2024,"publication_date":"2024-06-23","ids":{"openalex":"https://openalex.org/W4404133772","doi":"https://doi.org/10.1145/3649329.3657338"},"language":"en","primary_location":{"id":"doi:10.1145/3649329.3657338","doi":"https://doi.org/10.1145/3649329.3657338","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3649329.3657338","pdf_url":null,"source":{"id":"https://openalex.org/S4210231368","display_name":"ACM/IEEE Design Automation Conference (DAC)","issn_l":"0738-100X","issn":["0738-100X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 61st ACM/IEEE Design Automation Conference","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1145/3649329.3657338","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111061946","display_name":"Yuxuan Yin","orcid":"https://orcid.org/0009-0001-5504-3142","observed_orcids":["https://orcid.org/0009-0001-5504-3142"]},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuxuan Yin","raw_affiliation_strings":["University of California, Santa Barbara, CA, United States"],"raw_orcid":"https://orcid.org/0009-0001-5504-3142","affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, CA, United States","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044103702","display_name":"Rebecca Chen","orcid":"https://orcid.org/0009-0002-1616-6075","observed_orcids":["https://orcid.org/0009-0002-1616-6075"]},"institutions":[{"id":"https://openalex.org/I4210140035","display_name":"NXP (United States)","ror":"https://ror.org/054fc6480","country_code":"US","type":"company","lineage":["https://openalex.org/I109147379","https://openalex.org/I4210140035"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rebecca Chen","raw_affiliation_strings":["NXP Semiconductors, Austin, TX, United States"],"raw_orcid":"https://orcid.org/0009-0002-1616-6075","affiliations":[{"raw_affiliation_string":"NXP Semiconductors, Austin, TX, United States","institution_ids":["https://openalex.org/I4210140035"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105462297","display_name":"Chen He","orcid":"https://orcid.org/0000-0001-8100-0237","observed_orcids":["https://orcid.org/0000-0001-8100-0237"]},"institutions":[{"id":"https://openalex.org/I4210140035","display_name":"NXP (United States)","ror":"https://ror.org/054fc6480","country_code":"US","type":"company","lineage":["https://openalex.org/I109147379","https://openalex.org/I4210140035"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chen He","raw_affiliation_strings":["NXP Semiconductors, Austin, TX, United States"],"raw_orcid":"https://orcid.org/0000-0001-8100-0237","affiliations":[{"raw_affiliation_string":"NXP Semiconductors, Austin, TX, United States","institution_ids":["https://openalex.org/I4210140035"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100432782","display_name":"Peng Li","orcid":"https://orcid.org/0000-0003-3548-4589","observed_orcids":["https://orcid.org/0000-0003-3548-4589"]},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peng Li","raw_affiliation_strings":["University of California, Santa Barbara, CA, United States"],"raw_orcid":"https://orcid.org/0000-0003-3548-4589","affiliations":[{"raw_affiliation_string":"University of California, Santa Barbara, CA, United States","institution_ids":["https://openalex.org/I154570441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3363,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.71505622,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.3937999904155731,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.3937999904155731,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.3474000096321106,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.03689999878406525,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/conformal-prediction","display_name":"conformal prediction","score":0.9660000205039978},{"id":"https://openalex.org/keywords/interval-prediction","display_name":"interval prediction","score":0.9380000233650208},{"id":"https://openalex.org/keywords/minimum-operating-voltage","display_name":"minimum operating voltage","score":0.9309999942779541},{"id":"https://openalex.org/keywords/process-variation","display_name":"process variation","score":0.7559999823570251},{"id":"https://openalex.org/keywords/coverage-guarantees","display_name":"coverage guarantees","score":0.7409999966621399},{"id":"https://openalex.org/keywords/data-efficiency","display_name":"data efficiency","score":0.7239999771118164},{"id":"https://openalex.org/keywords/calibration","display_name":"calibration","score":0.6019999980926514},{"id":"https://openalex.org/keywords/manufacturing-testing","display_name":"manufacturing test","score":0.4699999988079071}],"concepts":[{"id":"https://openalex.org/C2778067643","wikidata":"https://www.wikidata.org/wiki/Q166507","display_name":"Interval (graph theory)","level":2,"score":0.6139575839042664},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5994530916213989},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5211477279663086},{"id":"https://openalex.org/C2983220686","wikidata":"https://www.wikidata.org/wiki/Q951437","display_name":"Interval data","level":3,"score":0.5128717422485352},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4971933662891388},{"id":"https://openalex.org/C67186912","wikidata":"https://www.wikidata.org/wiki/Q367664","display_name":"Data modeling","level":2,"score":0.41013944149017334},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.2522268295288086},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16485923528671265},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11763507127761841},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11188235878944397},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07483842968940735},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C2780009758","wikidata":"https://www.wikidata.org/wiki/Q6804172","display_name":"Measure (data warehouse)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1145/3649329.3657338","doi":"https://doi.org/10.1145/3649329.3657338","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3649329.3657338","pdf_url":null,"source":{"id":"https://openalex.org/S4210231368","display_name":"ACM/IEEE Design Automation Conference (DAC)","issn_l":"0738-100X","issn":["0738-100X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 61st ACM/IEEE Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":{"id":"doi:10.1145/3649329.3657338","doi":"https://doi.org/10.1145/3649329.3657338","is_oa":true,"landing_page_url":"https://doi.org/10.1145/3649329.3657338","pdf_url":null,"source":{"id":"https://openalex.org/S4210231368","display_name":"ACM/IEEE Design Automation Conference (DAC)","issn_l":"0738-100X","issn":["0738-100X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"conference"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 61st ACM/IEEE Design Automation Conference","raw_type":"proceedings-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.7207000255584717}],"study_designs":[],"awards":[{"id":"https://openalex.org/G6492328930","display_name":"Collaborative Research: SHF: Medium: Data-Efficient Uncovering of Rare Design Failures for Reliability-Critical Circuits","funder_award_id":"1956313","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1553101044","https://openalex.org/W2024260156","https://openalex.org/W2034368206","https://openalex.org/W2165363188","https://openalex.org/W2171585602","https://openalex.org/W2270670505","https://openalex.org/W2295598076","https://openalex.org/W3124406777","https://openalex.org/W3216141895","https://openalex.org/W4212774754"],"related_works":["https://openalex.org/W4401568737","https://openalex.org/W4411173397","https://openalex.org/W3216141895","https://openalex.org/W4312988666","https://openalex.org/W4390098557","https://openalex.org/W4413917145","https://openalex.org/W4415821984","https://openalex.org/W4410041774","https://openalex.org/W2946508874","https://openalex.org/W2998704098"],"abstract_inverted_index":{"Accurate":[0],"minimum":[1],"operating":[2],"voltage":[3],"(Vmin)":[4],"prediction":[5,62],"is":[6,81],"a":[7,24,46,77],"critical":[8],"element":[9],"in":[10,18,30,63],"manufacturing":[11],"tests.":[12],"Conventional":[13],"methods":[14],"lack":[15,47],"coverage":[16,33],"guarantees":[17,34],"interval":[19,36,61],"predictions.":[20,37],"Conformal":[21],"Prediction":[22],"(CP),":[23],"distribution-free":[25],"machine":[26],"learning":[27],"approach,":[28],"excels":[29],"providing":[31,58],"rigorous":[32],"for":[35,83],"However,":[38],"standard":[39],"CP":[40],"predictors":[41],"may":[42],"fail":[43],"due":[44],"to":[45],"of":[48,50,66,89],"knowledge":[49],"process":[51,67],"variations.":[52],"We":[53,85],"address":[54],"this":[55],"challenge":[56],"by":[57],"principled":[59],"conformalized":[60],"the":[64,74,87,90],"presence":[65],"variations":[68],"with":[69],"high":[70],"data":[71,75],"efficiency,":[72],"where":[73],"from":[76],"few":[78],"additional":[79],"chips":[80],"utilized":[82],"calibration.":[84],"demonstrate":[86],"superiority":[88],"proposed":[91],"method":[92],"on":[93],"industrial":[94],"16nm":[95],"chip":[96],"data.":[97]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2024-11-08T00:00:00"}