{"id":"https://openalex.org/W4403211908","doi":"https://doi.org/10.1109/icecsp61809.2024.10698724","title":"Design and Verification of High-Speed, Low-Power Flash ADC for Mixed Signal Applications","display_name":"Design and Verification of High-Speed, Low-Power Flash ADC for Mixed Signal Applications","publication_year":2024,"publication_date":"2024-08-08","ids":{"openalex":"https://openalex.org/W4403211908","doi":"https://doi.org/10.1109/icecsp61809.2024.10698724"},"language":"en","primary_location":{"id":"doi:10.1109/icecsp61809.2024.10698724","doi":"https://doi.org/10.1109/icecsp61809.2024.10698724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecsp61809.2024.10698724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5094362898","display_name":"Ajay Kumar Kapaka","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I70971781","display_name":"Dr. B. R. Ambedkar National Institute of Technology Jalandhar","ror":"https://ror.org/03xt0bg88","country_code":"IN","type":"education","lineage":["https://openalex.org/I70971781"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ajay Kumar Kapaka","raw_affiliation_strings":["DR B R Ambedkar National Institute of Technology,Jalandhar,Punjab"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DR B R Ambedkar National Institute of Technology,Jalandhar,Punjab","institution_ids":["https://openalex.org/I70971781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017623378","display_name":"Aijaz Mehdi Zaidi","orcid":"https://orcid.org/0000-0002-8794-4690","observed_orcids":["https://orcid.org/0000-0002-8794-4690","https://orcid.org/0000-0002-9071-7747"]},"institutions":[{"id":"https://openalex.org/I70971781","display_name":"Dr. B. R. Ambedkar National Institute of Technology Jalandhar","ror":"https://ror.org/03xt0bg88","country_code":"IN","type":"education","lineage":["https://openalex.org/I70971781"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Aijaz M.Zaidi","raw_affiliation_strings":["DR B R Ambedkar National Institute of Technology,Jalandhar,Punjab"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DR B R Ambedkar National Institute of Technology,Jalandhar,Punjab","institution_ids":["https://openalex.org/I70971781"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103135569","display_name":"Balwinder Raj","orcid":"https://orcid.org/0000-0003-4808-3768","observed_orcids":["https://orcid.org/0000-0003-4808-3768"]},"institutions":[{"id":"https://openalex.org/I70971781","display_name":"Dr. B. R. Ambedkar National Institute of Technology Jalandhar","ror":"https://ror.org/03xt0bg88","country_code":"IN","type":"education","lineage":["https://openalex.org/I70971781"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Balwinder Raj","raw_affiliation_strings":["DR B R Ambedkar National Institute of Technology,Jalandhar,Punjab"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DR B R Ambedkar National Institute of Technology,Jalandhar,Punjab","institution_ids":["https://openalex.org/I70971781"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I70971781"],"apc_list":null,"apc_paid":null,"fwci":1.9111,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.84827166,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0003000000142492354,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flash-adc","display_name":"flash ADC","score":0.8989999890327454},{"id":"https://openalex.org/keywords/analog-to-digital-converter","display_name":"analog-to-digital converter","score":0.9049999713897705},{"id":"https://openalex.org/keywords/mixed-signal-circuits","display_name":"mixed-signal circuits","score":0.6330000162124634},{"id":"https://openalex.org/keywords/systemverilog","display_name":"SystemVerilog","score":0.6150000095367432},{"id":"https://openalex.org/keywords/low-power-design","display_name":"low power design","score":0.6990000009536743},{"id":"https://openalex.org/keywords/high-speed-adc","display_name":"high-speed ADC","score":0.7549999952316284}],"concepts":[{"id":"https://openalex.org/C164862427","wikidata":"https://www.wikidata.org/wiki/Q2744647","display_name":"Flash ADC","level":4,"score":0.7224982976913452},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.6676366925239563},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6348627805709839},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.571186900138855},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.501211404800415},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.43706125020980835},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.35041379928588867},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1856015920639038},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.14734789729118347},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10019302368164062},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0826154351234436},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icecsp61809.2024.10698724","doi":"https://doi.org/10.1109/icecsp61809.2024.10698724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icecsp61809.2024.10698724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[{"score":0.8100000023841858,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W51782630","https://openalex.org/W1602755473","https://openalex.org/W2040438223","https://openalex.org/W2046177743","https://openalex.org/W2080017541","https://openalex.org/W2139636126","https://openalex.org/W2155332436","https://openalex.org/W2160614624","https://openalex.org/W2548163564","https://openalex.org/W2749342543","https://openalex.org/W2772200284","https://openalex.org/W2794169240","https://openalex.org/W2919546863","https://openalex.org/W2970518208","https://openalex.org/W3009722464","https://openalex.org/W3084952742","https://openalex.org/W4205685271","https://openalex.org/W4366978750"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W3084952742","https://openalex.org/W2742610530","https://openalex.org/W2214718483","https://openalex.org/W2148068418","https://openalex.org/W1992689052","https://openalex.org/W3028366910","https://openalex.org/W2545851693","https://openalex.org/W2132315124","https://openalex.org/W3140388444"],"abstract_inverted_index":{"Nowadays":[0],"modern":[1],"semiconductor":[2],"devices":[3],"and":[4,41,70,97,135,170,187],"system-on-chip":[5],"(SoC)'s":[6],"has":[7],"mixed":[8],"signal":[9,168],"(Intellectual":[10],"Property":[11],"(IP)'s.":[12],"So,":[13],"a":[14,31,48,53,89,105,120,176],"device":[15],"is":[16,109,130],"required":[17],"which":[18],"can":[19],"convert":[20],"one":[21],"form":[22],"of":[23,60,88,179],"data":[24],"into":[25,127],"another":[26],"form.":[27],"ADC":[28,196],"serves":[29],"as":[30,164],"bridge":[32],"between":[33],"the":[34,57,85,101,143,151,180,195],"analog":[35,63],"world":[36],"(sensor":[37],"capturing":[38],"real-world":[39],"signals)":[40],"digital":[42,79,117,165],"processing":[43],"units.":[44],"This":[45],"research":[46,82,173],"presents":[47],"detailed":[49],"design":[50],"methodology":[51],"for":[52,62,67,78,123,158],"Flash-type":[54],"ADC,":[55,91],"utilizing":[56,100],"collaborative":[58],"capabilities":[59],"Cadence":[61,144],"circuit":[64],"design,":[65],"SPICE":[66,148],"electrical":[68],"simulation,":[69],"System":[71,133],"Verilog":[72,134],"with":[73,137,175],"Real":[74],"Number":[75],"Modeling":[76],"(RNM)":[77],"verification.":[80],"The":[81,116,172],"focuses":[83],"on":[84],"architectural":[86],"optimization":[87],"flash":[90],"targeting":[92],"enhancements":[93],"in":[94,142,160,194],"speed,":[95,186],"power":[96,188],"efficiency":[98],"by":[99,147],"suitable":[102],"comparator.":[103],"Furthermore,":[104],"reference":[106],"voltage":[107],"ladder":[108],"also":[110],"designed":[111,131],"to":[112],"achieve":[113],"high":[114],"precision.":[115],"encoding":[118],"logic,":[119],"vital":[121],"component":[122],"translating":[124],"comparator":[125],"outputs":[126],"binary":[128],"code":[129],"using":[132],"modeled":[136],"RNM.":[138],"Extensive":[139],"simulations":[140],"conducted":[141],"environment,":[145],"corroborated":[146],"analyses,":[149],"demonstrate":[150],"ADC's":[152,181],"robust":[153],"performance,":[154],"confirming":[155],"its":[156,191],"potential":[157],"deployment":[159],"high-speed":[161],"applications":[162],"such":[163],"communication,":[166],"Mixed":[167],"IPs,":[169],"instrumentation.":[171],"culminates":[174],"comprehensive":[177],"evaluation":[178],"performance":[182],"metrics":[183],"including":[184],"Resolution,":[185],"consumption,":[189],"highlighting":[190],"competitive":[192],"edge":[193],"landscape.":[197]},"counts_by_year":[{"year":2025,"cited_by_count":2}],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2025-10-10T00:00:00"}
