{"id":"https://openalex.org/W4400034751","doi":"https://doi.org/10.1109/ectc51529.2024.00168","title":"Integrated Design Ecosystem for Chiplets Heterogeneous Integration and Chip-to-Chip Interconnects in Advanced Packaging Technology","display_name":"Integrated Design Ecosystem for Chiplets Heterogeneous Integration and Chip-to-Chip Interconnects in Advanced Packaging Technology","publication_year":2024,"publication_date":"2024-05-28","ids":{"openalex":"https://openalex.org/W4400034751","doi":"https://doi.org/10.1109/ectc51529.2024.00168"},"language":"en","primary_location":{"id":"doi:10.1109/ectc51529.2024.00168","doi":"https://doi.org/10.1109/ectc51529.2024.00168","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ectc51529.2024.00168","pdf_url":null,"source":{"id":"https://openalex.org/S4363608088","display_name":"IEEE Electronic Components and Technology Conference (ECTC)","issn_l":"2766-8401","issn":["2766-8401"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 74th Electronic Components and Technology Conference (ECTC)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101607358","display_name":"Lihong Cao","orcid":"https://orcid.org/0000-0002-3866-2734","observed_orcids":["https://orcid.org/0000-0002-3866-2734"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Lihong Cao","raw_affiliation_strings":["Advanced Semiconductor Engineering, Inc. (US),Engineering & Technical Promotion,Austin,US"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Semiconductor Engineering, Inc. (US),Engineering & Technical Promotion,Austin,US","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069952014","display_name":"Chen-Chao Wang","orcid":"https://orcid.org/0000-0002-7690-6656","observed_orcids":["https://orcid.org/0000-0002-7690-6656"]},"institutions":[{"id":"https://openalex.org/I2799432993","display_name":"Advanced Semiconductor Engineering (Taiwan)","ror":"https://ror.org/04rgfzt17","country_code":"TW","type":"company","lineage":["https://openalex.org/I2799432993"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chen-Chao Wang","raw_affiliation_strings":["Advanced Semiconductor Engineering, Inc,Corporate R&D Center,Kaohsiung,Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Semiconductor Engineering, Inc,Corporate R&D Center,Kaohsiung,Taiwan","institution_ids":["https://openalex.org/I2799432993"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102170840","display_name":"Chih-Yi Huang","orcid":"https://orcid.org/0009-0007-0605-5108","observed_orcids":["https://orcid.org/0009-0007-0605-5108"]},"institutions":[{"id":"https://openalex.org/I2799432993","display_name":"Advanced Semiconductor Engineering (Taiwan)","ror":"https://ror.org/04rgfzt17","country_code":"TW","type":"company","lineage":["https://openalex.org/I2799432993"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chih-Yi Huang","raw_affiliation_strings":["Advanced Semiconductor Engineering, Inc,Corporate R&D Center,Kaohsiung,Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Semiconductor Engineering, Inc,Corporate R&D Center,Kaohsiung,Taiwan","institution_ids":["https://openalex.org/I2799432993"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019134208","display_name":"Hung\u2010Chun Kuo","orcid":"https://orcid.org/0000-0003-1707-7138","observed_orcids":["https://orcid.org/0000-0003-1707-7138"]},"institutions":[{"id":"https://openalex.org/I2799432993","display_name":"Advanced Semiconductor Engineering (Taiwan)","ror":"https://ror.org/04rgfzt17","country_code":"TW","type":"company","lineage":["https://openalex.org/I2799432993"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hung-Chun Kuo","raw_affiliation_strings":["Advanced Semiconductor Engineering, Inc,Corporate R&D Center,Kaohsiung,Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Advanced Semiconductor Engineering, Inc,Corporate R&D Center,Kaohsiung,Taiwan","institution_ids":["https://openalex.org/I2799432993"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.7648,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.96090123,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1048","last_page":"1053"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.002199999988079071,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0007999999797903001,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chiplets","display_name":"chiplets","score":0.9739999771118164},{"id":"https://openalex.org/keywords/heterogeneous-integration","display_name":"heterogeneous integration","score":0.9229999780654907},{"id":"https://openalex.org/keywords/chip-to-chip-interconnects","display_name":"chip-to-chip interconnects","score":0.9779999852180481},{"id":"https://openalex.org/keywords/advanced-packaging","display_name":"advanced packaging","score":0.9079999923706055},{"id":"https://openalex.org/keywords/ucie","display_name":"UCIe","score":0.8069999814033508},{"id":"https://openalex.org/keywords/mechanical-analysis","display_name":"mechanical analysis","score":0.49900001287460327},{"id":"https://openalex.org/keywords/design-cycle-time","display_name":"design cycle time","score":0.4320000112056732}],"concepts":[{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.6420853734016418},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.6044732332229614},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49884653091430664},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4946736991405487},{"id":"https://openalex.org/C126233035","wikidata":"https://www.wikidata.org/wiki/Q5101572","display_name":"Chip-scale package","level":3,"score":0.48932474851608276},{"id":"https://openalex.org/C186260285","wikidata":"https://www.wikidata.org/wiki/Q759494","display_name":"Integrated circuit packaging","level":3,"score":0.47740498185157776},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40685346722602844},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.3773157000541687},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3330825865268707},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2494506537914276},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1354142725467682}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ectc51529.2024.00168","doi":"https://doi.org/10.1109/ectc51529.2024.00168","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ectc51529.2024.00168","pdf_url":null,"source":{"id":"https://openalex.org/S4363608088","display_name":"IEEE Electronic Components and Technology Conference (ECTC)","issn_l":"2766-8401","issn":["2766-8401"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 74th Electronic Components and Technology Conference (ECTC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4943999946117401}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2620776621","https://openalex.org/W2945577986","https://openalex.org/W2965769762","https://openalex.org/W3016874508","https://openalex.org/W3187104973","https://openalex.org/W4206431254"],"related_works":["https://openalex.org/W4385541699","https://openalex.org/W4411689015","https://openalex.org/W4401010883","https://openalex.org/W4309820330","https://openalex.org/W4361015538","https://openalex.org/W4410468008","https://openalex.org/W4414198101","https://openalex.org/W4283695399","https://openalex.org/W3080132014","https://openalex.org/W4408151522"],"abstract_inverted_index":{"As":[0],"chiplets":[1,90,120,177,201],"containing":[2],"multiple":[3],"diverse":[4,252],"functional":[5],"dies":[6],"are":[7,216],"integrated":[8],"into":[9],"a":[10,143,222,260],"single":[11,64],"package,":[12,400],"the":[13,30,75,89,98,112,171,181,193,206,292,302,322,366,384,394],"demand":[14],"for":[15,51,176,297,378],"advanced":[16,38,197,234,315,325,374],"packages":[17,39],"with":[18,129,158,274,339,347,359],"higher":[19,337],"density":[20],"interconnects":[21,175],"and":[22,33,54,73,78,85,94,104,107,117,134,141,147,167,191,200,213,241,285,295,317,383,399,404,407,413],"larger":[23],"footprint":[24],"body":[25],"sizes":[26],"has":[27,258],"surged.":[28],"However,":[29],"inherent":[31],"complexity":[32],"dense":[34],"connectivity":[35,79],"of":[36,101,114,173,196,208,324,362,370,396],"these":[37],"present":[40],"significant":[41,261],"challenges":[42],"when":[43],"employing":[44],"traditional":[45,99],"Electronic":[46],"Design":[47,225],"Automation":[48],"(EDA)":[49],"tools":[50],"packaging":[52,198,235,330],"design":[53,77,113,189,211,214,230,254,265,272,276,293,380],"assembly":[55,417],"manufacturing":[56,132,282],"validation.":[57],"Moreover,":[58],"as":[59,163],"chiplet-based":[60,379],"designs":[61,126,395],"transition":[62],"from":[63,184,202],"monolithic":[65],"die":[66],"to":[67,80,97,228,354,357],"multi-chiplet":[68],"configurations,":[69],"effectively":[70],"planning,":[71],"managing,":[72],"optimizing":[74],"top-level":[76],"achieve":[81],"optimal":[82],"performance,":[83],"power,":[84],"area":[86],"(PPA)":[87],"among":[88,119],"becomes":[91],"increasingly":[92],"challenging":[93],"complicated":[95],"compared":[96,356],"approach":[100],"separately":[102],"planning":[103],"executing":[105],"IC":[106,271],"package":[108,275],"layout":[109],"designs.":[110],"Furthermore,":[111],"interconnect":[115,155,298],"interfaces":[116,299],"protocols":[118],"is":[121,312,381,387],"also":[122,279,388],"very":[123],"crucial.":[124],"These":[125],"must":[127],"align":[128],"performance":[130,146,160,287,338,402],"expectation,":[131],"processes,":[133],"system":[135],"integration":[136,178],"requirements":[137],"while":[138,250,364],"ensuring":[139],"interoperability":[140],"maintaining":[142,365],"balance":[144],"between":[145],"flexibility.":[148],"Additionally,":[149,289],"different":[150,185],"application":[151],"domains":[152],"require":[153],"distinct":[154],"interfaces,":[156],"often":[157,179],"conflicting":[159],"indices":[161],"such":[162],"transmission":[164,368],"bandwidth,":[165],"latency,":[166],"power":[168],"consumption.":[169],"Especially,":[170],"use":[172],"die-to-die":[174],"takes":[180],"proprietary":[182],"links":[183],"customers,":[186],"thus":[187],"creating":[188],"boundaries":[190],"limiting":[192],"widespread":[194],"adoption":[195],"technology":[199],"various":[203,233],"suppliers.":[204],"Therefore,":[205],"development":[207],"new":[209],"system-level":[210],"methodologies":[212],"ecosystem":[215],"required.In":[217],"this":[218],"paper,":[219],"we":[220,290],"introduce":[221],"novel":[223],"Integrated":[224],"Ecosystem":[226],"(IDE)":[227],"enhance":[229],"flexibility":[231],"across":[232],"technologies":[236],"including":[237],"2.5D":[238],"Si":[239],"TSV":[240],"High":[242],"Density":[243],"Fanout":[244,327],"(HD":[245],"FO)":[246],"Redistribution":[247],"Layer":[248],"(RDL),":[249],"accommodating":[251],"customer":[253],"systems.":[255],"The":[256,332],"IDE":[257],"demonstrated":[259],"50%":[262],"improvement":[263],"in":[264,416],"cycle":[266],"time":[267],"by":[268,300],"seamlessly":[269],"integrating":[270],"tool":[273],"tools.":[277],"It":[278],"addresses":[280],"design-for":[281],"(DFM)":[283],"validation":[284],"electrical":[286,401],"considerations.":[288],"outline":[291],"considerations":[294],"specifications":[296],"leveraging":[301],"Universal":[303],"Chiplet":[304],"Interconnect":[305],"Express":[306],"(UCIe)":[307],"standard.":[308],"A":[309],"comparative":[310],"analysis":[311,376],"conducted":[313],"using":[314],"x32":[316,358],"x64":[318,340],"UCIe":[319],"standards":[320],"within":[321],"context":[323],"High-Density":[326],"Chip-on-Substrate":[328],"(FOCoS)":[329],"technology.":[331],"results":[333],"demonstrate":[334],"that":[335],"achieving":[336],"need":[341],"more":[342],"complex":[343],"RDL":[344,350,360,397],"signal":[345],"routing":[346],"significantly":[348],"smaller":[349],"land/space":[351],"(L/S)":[352],"down":[353],"1.7/1.7um,":[355],"L/S":[361],"2/2um":[363],"consistent":[367],"speed":[369],"32Gbps.":[371],"Finally,":[372],"an":[373],"mechanical":[375,406],"workflow":[377],"proposed":[382],"turnkey":[385],"toolbox":[386,392],"presented.":[389],"This":[390],"comprehensive":[391],"encompasses":[393],"interposer":[398],"modeling":[403],"simulation,":[405],"thermal":[408],"stress":[409],"analysis,":[410],"material":[411],"selection,":[412],"reliability":[414],"testing":[415],"production.":[418]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":3}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2024-06-27T00:00:00"}