{"id":"https://openalex.org/W4396759223","doi":"https://doi.org/10.1109/icdcot61034.2024.10515488","title":"Analysis of CMOS Full Adder Circuits for Multiplier Logic Architectures","display_name":"Analysis of CMOS Full Adder Circuits for Multiplier Logic Architectures","publication_year":2024,"publication_date":"2024-03-15","ids":{"openalex":"https://openalex.org/W4396759223","doi":"https://doi.org/10.1109/icdcot61034.2024.10515488"},"language":"en","primary_location":{"id":"doi:10.1109/icdcot61034.2024.10515488","doi":"https://doi.org/10.1109/icdcot61034.2024.10515488","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icdcot61034.2024.10515488","pdf_url":null,"source":{"id":"https://openalex.org/S7407096953","display_name":"International Conference on Distributed Computing and Optimization Techniques (ICDCOT)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 International Conference on Distributed Computing and Optimization Techniques (ICDCOT)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111191926","display_name":"Jyothi Ganesh Reddy","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405261004","display_name":"Sri Venkateswara College of Engineering Tirupati","ror":"https://ror.org/04m245a70","country_code":"IN","type":"education","lineage":["https://openalex.org/I4405261004"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jyothi Ganesh Reddy","raw_affiliation_strings":["Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","institution_ids":["https://openalex.org/I4405261004"]},{"raw_affiliation_string":"Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India","institution_ids":["https://openalex.org/I4405261004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083897962","display_name":"K. Lokesh Krishna","orcid":"https://orcid.org/0000-0002-0244-7055","observed_orcids":["https://orcid.org/0000-0002-0244-7055"]},"institutions":[{"id":"https://openalex.org/I4405261004","display_name":"Sri Venkateswara College of Engineering Tirupati","ror":"https://ror.org/04m245a70","country_code":"IN","type":"education","lineage":["https://openalex.org/I4405261004"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"K. Lokesh Krishna","raw_affiliation_strings":["Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","institution_ids":["https://openalex.org/I4405261004"]},{"raw_affiliation_string":"Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India","institution_ids":["https://openalex.org/I4405261004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093916980","display_name":"Jinka Priyanka Keerthi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405261004","display_name":"Sri Venkateswara College of Engineering Tirupati","ror":"https://ror.org/04m245a70","country_code":"IN","type":"education","lineage":["https://openalex.org/I4405261004"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Jinka Priyanka Keerthi","raw_affiliation_strings":["Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","institution_ids":["https://openalex.org/I4405261004"]},{"raw_affiliation_string":"Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India","institution_ids":["https://openalex.org/I4405261004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093916981","display_name":"Karamala Revanth","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405261004","display_name":"Sri Venkateswara College of Engineering Tirupati","ror":"https://ror.org/04m245a70","country_code":"IN","type":"education","lineage":["https://openalex.org/I4405261004"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Karamala Revanth","raw_affiliation_strings":["Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","institution_ids":["https://openalex.org/I4405261004"]},{"raw_affiliation_string":"Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India","institution_ids":["https://openalex.org/I4405261004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113202257","display_name":"Kalluri Sai Deekshitha","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405261004","display_name":"Sri Venkateswara College of Engineering Tirupati","ror":"https://ror.org/04m245a70","country_code":"IN","type":"education","lineage":["https://openalex.org/I4405261004"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kalluri Sai Deekshitha","raw_affiliation_strings":["Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sri Venkateswara College of Engineering,Department of ECE,Tirupati,Andhra Pradesh,India","institution_ids":["https://openalex.org/I4405261004"]},{"raw_affiliation_string":"Department of ECE, Sri Venkateswara College of Engineering, Tirupati, Andhra Pradesh, India","institution_ids":["https://openalex.org/I4405261004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5025630165","display_name":"Birasalapati Doraswamy","orcid":"https://orcid.org/0000-0001-6073-1145","observed_orcids":["https://orcid.org/0000-0001-6073-1145"]},"institutions":[{"id":"https://openalex.org/I4210124021","display_name":"Bule Hora University","ror":"https://ror.org/038n8fg68","country_code":"ET","type":"education","lineage":["https://openalex.org/I4210124021"]}],"countries":["ET"],"is_corresponding":false,"raw_author_name":"B. Doraswamy","raw_affiliation_strings":["College of Engineering & Technology, Bule Hora University,Department of Electrical & Computer Engineering,Ethiopia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Engineering & Technology, Bule Hora University,Department of Electrical & Computer Engineering,Ethiopia","institution_ids":["https://openalex.org/I4210124021"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.6771,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.9567534,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":95,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/full-adder","display_name":"full adder","score":0.9150000214576721},{"id":"https://openalex.org/keywords/cmos-logic-circuits","display_name":"CMOS logic circuits","score":0.7850000262260437},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"pass transistor logic","score":0.8330000042915344},{"id":"https://openalex.org/keywords/gate-diffusion-input-logic","display_name":"gate diffusion input logic","score":0.7129999995231628},{"id":"https://openalex.org/keywords/transmission-gate-logic","display_name":"transmission gate logic","score":0.8399999737739563},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"arithmetic logic unit","score":0.7799999713897705},{"id":"https://openalex.org/keywords/power-delay-product","display_name":"power-delay product","score":0.8429999947547913},{"id":"https://openalex.org/keywords/power-dissipation","display_name":"power dissipation","score":0.7730000019073486},{"id":"https://openalex.org/keywords/critical-path-delay","display_name":"critical path delay","score":0.7149999737739563}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.831481397151947},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5861335396766663},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5606264472007751},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5425835251808167},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.5396068692207336},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5351788401603699},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5207945704460144},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.47232455015182495},{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.4688877761363983},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.4516753554344177},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4502066671848297},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4385886490345001},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.39110293984413147},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38122811913490295},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.33746790885925293},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2385108470916748},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icdcot61034.2024.10515488","doi":"https://doi.org/10.1109/icdcot61034.2024.10515488","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icdcot61034.2024.10515488","pdf_url":null,"source":{"id":"https://openalex.org/S7407096953","display_name":"International Conference on Distributed Computing and Optimization Techniques (ICDCOT)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 International Conference on Distributed Computing and Optimization Techniques (ICDCOT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4943999946117401,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1575022128","https://openalex.org/W1633471522","https://openalex.org/W2068835049","https://openalex.org/W2791867184","https://openalex.org/W2811482481","https://openalex.org/W2913880649","https://openalex.org/W3162163331","https://openalex.org/W3194437664","https://openalex.org/W3207733856","https://openalex.org/W4323045097","https://openalex.org/W4366978652","https://openalex.org/W4385319257"],"related_works":["https://openalex.org/W7161601368","https://openalex.org/W7154221033","https://openalex.org/W4385319257","https://openalex.org/W7115571779","https://openalex.org/W4392054316","https://openalex.org/W7217586622","https://openalex.org/W6930850067","https://openalex.org/W4405633448","https://openalex.org/W2221192038","https://openalex.org/W2329434788"],"abstract_inverted_index":{"High":[0],"efficient":[1],"digital":[2],"adder":[3,21,48,80,107,150],"logic":[4,26,49,81,111,175],"circuits":[5,63,82,126],"are":[6,83,152],"very":[7,72],"essential":[8],"and":[9,15,34,59,68,108,115,137,189,196],"critical":[10,131],"modules":[11],"in":[12,23,117,160],"the":[13,125,172],"processor":[14],"controller":[16],"architectures.":[17],"For":[18],"example,":[19],"an":[20,24,42],"circuit":[22,28,119,187],"arithmetic":[25],"unit":[27],"must":[29],"offer":[30],"high":[31],"speed":[32],"operation":[33],"low":[35],"power":[36,135,142,178,203],"per":[37],"calculation":[38],"to":[39,53,124,127,185,202],"make":[40],"it":[41],"optimized":[43],"processor.":[44],"Apart":[45],"from":[46],"this,":[47],"is":[50,190],"also":[51],"used":[52],"carry":[54],"out":[55],"subtract":[56],"operations,":[57],"multiply":[58],"division":[60],"operations.":[61,78],"Logic":[62],"such":[64,89],"as":[65,90],"Full":[66,79],"adders":[67],"multipliers":[69],"have":[70,122],"become":[71],"elementary":[73],"components":[74],"of":[75,141,164,181],"signal":[76],"processing":[77],"implemented":[84],"by":[85],"using":[86,100,192],"different":[87,101],"technologies":[88,121],"conventional":[91,186],"complementary":[92],"metal":[93],"oxide":[94],"semiconductor":[95],"transistors,":[96],"transmission":[97],"gate":[98,104],"logic,":[99],"transistor":[102,110,174,194],"counts,":[103],"diffusion":[105],"input":[106],"pass":[109,173],"based":[112],"circuits.":[113],"Improvements":[114],"scaling":[116],"integrated":[118],"design":[120,162],"led":[123],"operate":[128],"at":[129,154],"less":[130,134,139],"path":[132],"delay,":[133],"consumption":[136],"final":[138],"values":[140],"delay":[143,204],"product.":[144],"In":[145],"this":[146],"work,":[147],"two":[148],"full":[149],"logics":[151],"simulated":[153],"0.09":[155],"micrometer":[156],"CMOS":[157],"process":[158],"technology":[159],"analog":[161],"environment":[163],"cadence":[165],"tools.":[166],"The":[167],"simulation":[168],"results":[169],"shows":[170],"that":[171],"offers":[176],"a":[177],"dissipation":[179],"reduction":[180],"18.46%":[182],"when":[183],"compared":[184],"topologies":[188],"designed":[191],"fourteen":[193],"count,":[195],"contributes":[197],"better":[198],"performance":[199],"with":[200],"respect":[201],"product":[205],"values.":[206]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2024,"cited_by_count":3}],"updated_date":"2026-11-10T11:39:43.021295","created_date":"2024-05-09T00:00:00"}
