{"id":"https://openalex.org/W4394895262","doi":"https://doi.org/10.1109/esci59607.2024.10497455","title":"Optimized Vedic Multiplier Using 3nm Nanosheet Technology","display_name":"Optimized Vedic Multiplier Using 3nm Nanosheet Technology","publication_year":2024,"publication_date":"2024-03-05","ids":{"openalex":"https://openalex.org/W4394895262","doi":"https://doi.org/10.1109/esci59607.2024.10497455"},"language":"en","primary_location":{"id":"doi:10.1109/esci59607.2024.10497455","doi":"https://doi.org/10.1109/esci59607.2024.10497455","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esci59607.2024.10497455","pdf_url":null,"source":{"id":"https://openalex.org/S4306498845","display_name":"International Conference on Emerging Smart Computing and Informatics (ESCI)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 International Conference on Emerging Smart Computing and Informatics (ESCI)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021121536","display_name":"Swati S. Shetkar","orcid":"https://orcid.org/0000-0002-2770-7829","observed_orcids":["https://orcid.org/0000-0002-2770-7829"]},"institutions":[{"id":"https://openalex.org/I4210146358","display_name":"Raisoni Group of Institutions","ror":"https://ror.org/03dp11s58","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210146358"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Swati S. Shetkar","raw_affiliation_strings":["G.H Raisoni College of Engineering and Management,Department of ECE,Pune,Maharashtra,India","Department of ECE, G.H Raisoni College of Engineering and Management, Pune, Maharashtra, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"G.H Raisoni College of Engineering and Management,Department of ECE,Pune,Maharashtra,India","institution_ids":[]},{"raw_affiliation_string":"Department of ECE, G.H Raisoni College of Engineering and Management, Pune, Maharashtra, India","institution_ids":["https://openalex.org/I4210146358"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032082506","display_name":"Sanjay Mahadev Koli","orcid":"https://orcid.org/0000-0001-5401-959X","observed_orcids":["https://orcid.org/0000-0001-5401-959X"]},"institutions":[{"id":"https://openalex.org/I4403386594","display_name":"Ajeenkya DY Patil University","ror":"https://ror.org/02v423c65","country_code":"IN","type":"education","lineage":["https://openalex.org/I4403386594"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sanjay Koli","raw_affiliation_strings":["Ajinkya D Y Patil School of Engineering,Department of ECE,Pune,Maharashtra,India","Department of ECE, Ajinkya D Y Patil School of Engineering, Pune, Maharashtra, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ajinkya D Y Patil School of Engineering,Department of ECE,Pune,Maharashtra,India","institution_ids":["https://openalex.org/I4403386594"]},{"raw_affiliation_string":"Department of ECE, Ajinkya D Y Patil School of Engineering, Pune, Maharashtra, India","institution_ids":["https://openalex.org/I4403386594"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3363,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.71505622,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.003100000089034438,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0006000000284984708,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vedic-multiplier","display_name":"Vedic multiplier","score":0.9789999723434448},{"id":"https://openalex.org/keywords/nanosheet-fet","display_name":"nanosheet FET","score":0.9409999847412109},{"id":"https://openalex.org/keywords/3-nm-technology-node","display_name":"3 nm technology node","score":0.871999979019165},{"id":"https://openalex.org/keywords/energy-consumption-reduction","display_name":"energy consumption reduction","score":0.531000018119812},{"id":"https://openalex.org/keywords/area-efficiency","display_name":"area efficiency","score":0.4410000145435333},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"arithmetic logic unit","score":0.7950000166893005},{"id":"https://openalex.org/keywords/low-leakage-current","display_name":"low leakage current","score":0.5709999799728394},{"id":"https://openalex.org/keywords/post-layout-simulation","display_name":"post-layout simulation","score":0.453000009059906}],"concepts":[{"id":"https://openalex.org/C51967427","wikidata":"https://www.wikidata.org/wiki/Q17148232","display_name":"Nanosheet","level":2,"score":0.7811431884765625},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5293995141983032},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44369080662727356},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.2591538429260254},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.15066596865653992},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esci59607.2024.10497455","doi":"https://doi.org/10.1109/esci59607.2024.10497455","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esci59607.2024.10497455","pdf_url":null,"source":{"id":"https://openalex.org/S4306498845","display_name":"International Conference on Emerging Smart Computing and Informatics (ESCI)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 International Conference on Emerging Smart Computing and Informatics (ESCI)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2085206436","https://openalex.org/W2290642284","https://openalex.org/W2896009780","https://openalex.org/W2912714324","https://openalex.org/W4285226249","https://openalex.org/W4285773446","https://openalex.org/W4387455777"],"related_works":["https://openalex.org/W7214749718","https://openalex.org/W4409118099","https://openalex.org/W4285226249","https://openalex.org/W3092318867","https://openalex.org/W3047618043","https://openalex.org/W3208452276","https://openalex.org/W4385452287","https://openalex.org/W4309639899","https://openalex.org/W2019335136","https://openalex.org/W2765720644"],"abstract_inverted_index":{"Nanosheet":[0],"FET":[1],"technology":[2,10,78,97],"is":[3,32,46],"an":[4,33],"alternative":[5],"to":[6,28,150],"FinFET":[7],"and":[8,17,25,63,140],"CMOS":[9,29],"as":[11],"it":[12],"gives":[13],"low":[14,18],"leakage":[15],"current":[16,109],"power":[19,62,147],"consumption.":[20],"NS-FET":[21,77],"has":[22],"better":[23],"mobility":[24],"scaling":[26],"compared":[27,149],"technology.":[30],"Multiplier":[31,137],"important":[34],"arithmetic":[35,41,72],"circuit":[36],"required":[37],"in":[38,79,87],"many":[39],"digital":[40],"applications.":[42],"Area,":[43],"power-efficient":[44],"multiplier":[45,124],"the":[47,68,108,119,131,141,151],"need":[48],"of":[49,70,74,102,118,135],"ALU.":[50],"Vedic":[51,71,123,136],"sutras":[52],"not":[53],"only":[54],"reduce":[55],"hardware":[56],"but":[57],"also":[58],"improve":[59],"parameters":[60,104],"like":[61],"delay.":[64],"This":[65],"paper":[66],"explains":[67],"implementation":[69],"circuits":[73],"3":[75,93],"nm":[76,94],"physical":[80],"layout.":[81,99],"The":[82,100,116],"proposed":[83,132,142],"designs":[84],"are":[85,105,125],"implemented":[86],"Micro":[88],"wind":[89],"EDA":[90],"3.9":[91],"with":[92],"deep":[95],"submicron":[96],"post":[98],"values":[101],"model":[103,114],"used":[106],"from":[107],"Berkeley":[110],"4":[111],"short":[112],"channel":[113],"(BSIM-CMG).":[115],"performances":[117],"Ex-OR":[120],"gate,":[121],"2-bit":[122],"analyzed.":[126],"Analyzed":[127],"results":[128],"show":[129],"that":[130],"I":[133],"design":[134,144],"shows":[138,145],"96.40%":[139],"II":[143],"117.82%":[146],"reduction":[148],"14nm":[152],"VM.":[153]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2024-04-18T00:00:00"}