{"id":"https://openalex.org/W4387849321","doi":"https://doi.org/10.2478/jee-2023-0048","title":"Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider","display_name":"Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider","publication_year":2023,"publication_date":"2023-10-01","ids":{"openalex":"https://openalex.org/W4387849321","doi":"https://doi.org/10.2478/jee-2023-0048"},"language":"en","primary_location":{"id":"doi:10.2478/jee-2023-0048","doi":"https://doi.org/10.2478/jee-2023-0048","is_oa":true,"landing_page_url":"https://doi.org/10.2478/jee-2023-0048","pdf_url":"https://sciendo.com/pdf/10.2478/jee-2023-0048","source":{"id":"https://openalex.org/S4210190933","display_name":"Journal of Electrical Engineering","issn_l":"1335-3632","issn":["1335-3632","1339-309X"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-c","poland-40","russia-white-list-3"],"host_organization":"https://openalex.org/P4310313990","host_organization_name":"De Gruyter","host_organization_lineage":["https://openalex.org/P4310313990"],"host_organization_lineage_names":["De Gruyter"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Electrical Engineering","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://sciendo.com/pdf/10.2478/jee-2023-0048","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006541003","display_name":"B. S. Premananda","orcid":"https://orcid.org/0000-0001-7740-7659","observed_orcids":["https://orcid.org/0000-0001-7740-7659"]},"institutions":[{"id":"https://openalex.org/I4389425378","display_name":"R.V. College of Engineering","ror":"https://ror.org/041re0e60","country_code":"IN","type":"education","lineage":["https://openalex.org/I4389425378"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Premananda Belegehalli Siddaiah","raw_affiliation_strings":["Department of Electronics and Telecommunication Engineering RV College of Engineering , Bengaluru , India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Engineering RV College of Engineering , Bengaluru , India","institution_ids":["https://openalex.org/I4389425378"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093106537","display_name":"Sahithi Narsepalli","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4389425378","display_name":"R.V. College of Engineering","ror":"https://ror.org/041re0e60","country_code":"IN","type":"education","lineage":["https://openalex.org/I4389425378"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sahithi Narsepalli","raw_affiliation_strings":["Department of Electronics and Telecommunication Engineering RV College of Engineering , Bengaluru , India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Engineering RV College of Engineering , Bengaluru , India","institution_ids":["https://openalex.org/I4389425378"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110975598","display_name":"Sanya Mittal","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4389425378","display_name":"R.V. College of Engineering","ror":"https://ror.org/041re0e60","country_code":"IN","type":"education","lineage":["https://openalex.org/I4389425378"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sanya Mittal","raw_affiliation_strings":["Department of Electronics and Telecommunication Engineering RV College of Engineering , Bengaluru , India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Engineering RV College of Engineering , Bengaluru , India","institution_ids":["https://openalex.org/I4389425378"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101466247","display_name":"Abdur Rehman","orcid":"https://orcid.org/0000-0001-7214-5733","observed_orcids":["https://orcid.org/0000-0001-7214-5733"]},"institutions":[{"id":"https://openalex.org/I4389425378","display_name":"R.V. College of Engineering","ror":"https://ror.org/041re0e60","country_code":"IN","type":"education","lineage":["https://openalex.org/I4389425378"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Abdur Rehman","raw_affiliation_strings":["Department of Electronics and Telecommunication Engineering RV College of Engineering , Bengaluru , India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunication Engineering RV College of Engineering , Bengaluru , India","institution_ids":["https://openalex.org/I4389425378"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5006541003"],"corresponding_institution_ids":["https://openalex.org/I4389425378"],"apc_list":null,"apc_paid":null,"fwci":0.6414,"has_fulltext":true,"cited_by_count":9,"citation_normalized_percentile":{"value":0.59613381,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":"74","issue":"5","first_page":"403","last_page":"412"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.6265000104904175,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.6265000104904175,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.3610999882221222,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.006000000052154064,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dual-modulus-prescaler","display_name":"dual-modulus prescaler","score":0.8209999799728394},{"id":"https://openalex.org/keywords/frequency-divider","display_name":"frequency divider","score":0.8050000071525574},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"pass transistor logic","score":0.9399999976158142},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"phase-locked loop","score":0.7329999804496765},{"id":"https://openalex.org/keywords/d-flip-flop","display_name":"D flip-flop","score":0.703000009059906},{"id":"https://openalex.org/keywords/energy-consumption-reduction","display_name":"energy consumption reduction","score":0.7409999966621399},{"id":"https://openalex.org/keywords/area-efficiency","display_name":"area efficiency","score":0.6940000057220459},{"id":"https://openalex.org/keywords/cmos-180-nm","display_name":"CMOS 180 nm","score":0.8209999799728394}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6256902813911438},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.577104389667511},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5426623225212097},{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.5317078232765198},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.49831295013427734},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4963875412940979},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4920305907726288},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48184478282928467},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47779494524002075},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.441441148519516},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.42310813069343567},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4120391011238098},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3323586583137512},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2569344639778137},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1707017719745636},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.07052281498908997},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.2478/jee-2023-0048","doi":"https://doi.org/10.2478/jee-2023-0048","is_oa":true,"landing_page_url":"https://doi.org/10.2478/jee-2023-0048","pdf_url":"https://sciendo.com/pdf/10.2478/jee-2023-0048","source":{"id":"https://openalex.org/S4210190933","display_name":"Journal of Electrical Engineering","issn_l":"1335-3632","issn":["1335-3632","1339-309X"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-c","poland-40","russia-white-list-3"],"host_organization":"https://openalex.org/P4310313990","host_organization_name":"De Gruyter","host_organization_lineage":["https://openalex.org/P4310313990"],"host_organization_lineage_names":["De Gruyter"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Electrical Engineering","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.2478/jee-2023-0048","doi":"https://doi.org/10.2478/jee-2023-0048","is_oa":true,"landing_page_url":"https://doi.org/10.2478/jee-2023-0048","pdf_url":"https://sciendo.com/pdf/10.2478/jee-2023-0048","source":{"id":"https://openalex.org/S4210190933","display_name":"Journal of Electrical Engineering","issn_l":"1335-3632","issn":["1335-3632","1339-309X"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-c","poland-40","russia-white-list-3"],"host_organization":"https://openalex.org/P4310313990","host_organization_name":"De Gruyter","host_organization_lineage":["https://openalex.org/P4310313990"],"host_organization_lineage_names":["De Gruyter"],"type":"journal"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Electrical Engineering","raw_type":"journal-article"},"sustainable_development_goals":[{"score":0.651199996471405,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4387849321.pdf","grobid_xml":"https://content.openalex.org/works/W4387849321.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W2056392994","https://openalex.org/W2070759215","https://openalex.org/W2099631106","https://openalex.org/W2184634778","https://openalex.org/W2725405098","https://openalex.org/W3102163417","https://openalex.org/W3200306374","https://openalex.org/W3217616230","https://openalex.org/W4205338271","https://openalex.org/W4300960370","https://openalex.org/W4376609146","https://openalex.org/W4378388131"],"related_works":["https://openalex.org/W4376609146","https://openalex.org/W4378388131","https://openalex.org/W7163888465","https://openalex.org/W4205338271","https://openalex.org/W4376614169","https://openalex.org/W4295127399","https://openalex.org/W1569620699","https://openalex.org/W2947664323","https://openalex.org/W3020912213","https://openalex.org/W2023877820"],"abstract_inverted_index":{"Abstract":[0],"Pre-scalers":[1],"are":[2,185,199,239],"electronic":[3],"circuits":[4,30,184,205],"used":[5,85],"in":[6,86,113,121,157,208,219,252],"phase-locked":[7],"loops":[8],"to":[9,32,68,74,172,215,232],"multiply":[10],"frequencies.":[11],"This":[12,94],"is":[13],"achieved":[14],"by":[15,180],"dividing":[16],"the":[17,54,62,75,78,87,114,158,173,209,217,220,233],"high-frequency":[18,26],"signals":[19],"generated":[20],"from":[21],"a":[22,143,165,188],"voltage-controlled":[23],"oscillator.":[24],"The":[25,50,104,128,148,182,201,236],"operation":[27],"of":[28,77,126,146,169,227],"pre-scaler":[29,253],"leads":[31],"significantly":[33],"higher":[34],"power":[35,70,124,144,167,225,250],"consumption.":[36,71],"To":[37],"address":[38],"this,":[39],"D":[40],"flip-flops":[41],"(D-FF)":[42],"realized":[43,186,207],"using":[44,187],"true-single":[45],"phase":[46],"clocking":[47],"(TSPC)":[48],"logic.":[49],"work":[51],"suggests":[52],"incorporating":[53],"Adaptive":[55],"Voltage":[56],"Level":[57],"Source":[58],"(AVLS)":[59],"circuit":[60,67,176],"with":[61,111,135,155],"Dual":[63],"Modulus":[64],"Pre-Scaler":[65],"(DMPS)":[66],"reduce":[69],"In":[72],"addition":[73],"incorporation":[76],"AVLS":[79,118,140,162],"circuit,":[80,119,141,163],"pass":[81],"transistor":[82,178],"logic":[83,136],"(PTL)":[84],"feedback,":[88],"further":[89],"minimizes":[90],"transistors":[91],"and":[92,116,138,160,177,196,242],"power.":[93],"paper":[95],"proposes":[96],"three":[97],"different":[98],"designs":[99,238],"for":[100,248],"divide-by-32/33":[101,203],"DMPS":[102,175,204],"circuit.":[103,235],"proposed-1":[105],"design":[106,130,150],"combines":[107],"regular":[108],"TSPC-based":[109,133,153],"D-FF":[110,134,154],"PTL":[112,156],"feedback":[115,159],"an":[117,122,139,161],"resulting":[120],"average":[123],"reduction":[125,145,168,226],"36.5%.":[127],"proposed-2":[129],"employs":[131,151],"split-path":[132,152],"gates":[137],"achieving":[142,164],"46.9%.":[147],"proposed-3":[149],"significant":[166],"47.8%":[170],"compared":[171,231],"existing":[174],"count":[179],"9.1%.":[181],"proposed":[183,202,237],"CMOS":[189,210],"180":[190],"nm":[191,212],"technology":[192,213,222],"node.":[193,223],"Cadence":[194],"Virtuoso":[195],"Spectre":[197],"tools":[198],"used.":[200],"also":[206],"45":[211],"node":[214],"verify":[216],"functionality":[218],"lower":[221],"A":[224],"46.86%":[228],"observed":[229],"when":[230],"reference":[234],"both":[240],"power-":[241],"area-efficient,":[243],"making":[244],"them":[245],"promising":[246],"solutions":[247],"minimizing":[249],"consumption":[251],"circuits.":[254]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":2}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2023-10-22T00:00:00"}