{"id":"https://openalex.org/W4366265279","doi":"https://doi.org/10.55524/ijircst.2023.11.2.11","title":"Verification of UART and I2C Protocols Using System Verilog","display_name":"Verification of UART and I2C Protocols Using System Verilog","publication_year":2023,"publication_date":"2023-03-01","ids":{"openalex":"https://openalex.org/W4366265279","doi":"https://doi.org/10.55524/ijircst.2023.11.2.11"},"language":"en","primary_location":{"id":"doi:10.55524/ijircst.2023.11.2.11","doi":"https://doi.org/10.55524/ijircst.2023.11.2.11","is_oa":true,"landing_page_url":"https://doi.org/10.55524/ijircst.2023.11.2.11","pdf_url":"http://dx.doi.org/10.55524/ijircst.2023.11.2.11","source":{"id":"https://openalex.org/S4210230306","display_name":"International Journal of Innovative Research in Computer Science & Technology","issn_l":"2347-5552","issn":["2347-5552"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Innovative Research in Computer Science and Technology","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"http://dx.doi.org/10.55524/ijircst.2023.11.2.11","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075273124","display_name":"Ch. Manohar Kumar","orcid":"https://orcid.org/0000-0003-1135-4974","observed_orcids":["https://orcid.org/0000-0003-1135-4974"]},"institutions":[{"id":"https://openalex.org/I4405265901","display_name":"Gayatri Vidya Parishad College for Degree and PG Courses (Autonomous)","ror":"https://ror.org/00shrhd51","country_code":"IN","type":"education","lineage":["https://openalex.org/I4405265901"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Dr. Ch. Manohar Kumar","raw_affiliation_strings":["Assistant Professor, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree and PG Courses(A), Visakhapatnam, Andhra Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Assistant Professor, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree and PG Courses(A), Visakhapatnam, Andhra Pradesh, India","institution_ids":["https://openalex.org/I4405265901"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082723610","display_name":"G. Mahesh Babu","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"G. Mahesh Babu","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5017179203","display_name":"A. Hemanth Chakradhar","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Hemanth Chakradhar","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034957978","display_name":"A.S.K. Pranav","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A.S.K. Pranav","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065023935","display_name":"D. Sudheer","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D. Sudheer","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5055426106","display_name":"U. Alex Prince","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405265901","display_name":"Gayatri Vidya Parishad College for Degree and PG Courses (Autonomous)","ror":"https://ror.org/00shrhd51","country_code":"IN","type":"education","lineage":["https://openalex.org/I4405265901"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"U. Alex Prince","raw_affiliation_strings":["Student, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree andPG Courses(A), Visakhapatnam, Andhra Pradesh, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Student, Department of Electronics and Communication Engineering, Gayatri Vidya Parishad College for Degree andPG Courses(A), Visakhapatnam, Andhra Pradesh, India","institution_ids":["https://openalex.org/I4405265901"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2851,"has_fulltext":true,"cited_by_count":4,"citation_normalized_percentile":{"value":0.41400734,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":96},"biblio":{"volume":"11","issue":"2","first_page":"58","last_page":"61"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.6015999913215637,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.6015999913215637,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.2687999904155731,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.0812000036239624,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/uart","display_name":"UART","score":0.7319999933242798},{"id":"https://openalex.org/keywords/i2c","display_name":"I2C","score":0.9829999804496765},{"id":"https://openalex.org/keywords/systemverilog","display_name":"SystemVerilog","score":0.7639999985694885},{"id":"https://openalex.org/keywords/design-verification","display_name":"design verification","score":0.7329999804496765},{"id":"https://openalex.org/keywords/vlsi","display_name":"VLSI","score":0.8109999895095825},{"id":"https://openalex.org/keywords/serial-communication-protocol","display_name":"serial communication protocol","score":0.746999979019165},{"id":"https://openalex.org/keywords/test-bench","display_name":"test bench","score":0.7760000228881836},{"id":"https://openalex.org/keywords/functional-coverage","display_name":"functional coverage","score":0.6759999990463257},{"id":"https://openalex.org/keywords/constrained-randomization","display_name":"constrained randomization","score":0.800000011920929},{"id":"https://openalex.org/keywords/master-slave-communication","display_name":"master-slave communication","score":0.7350000143051147}],"concepts":[{"id":"https://openalex.org/C161911788","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Universal asynchronous receiver/transmitter","level":3,"score":0.8246012926101685},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8082919716835022},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.733027994632721},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5298891663551331},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4625833034515381},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.46240952610969543},{"id":"https://openalex.org/C12269588","wikidata":"https://www.wikidata.org/wiki/Q132364","display_name":"Communications protocol","level":2,"score":0.4605838656425476},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.44780999422073364},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4414999186992645},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4091329574584961},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.34846562147140503},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3412237763404846},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.24789583683013916},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.20003053545951843},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12421360611915588},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.55524/ijircst.2023.11.2.11","doi":"https://doi.org/10.55524/ijircst.2023.11.2.11","is_oa":true,"landing_page_url":"https://doi.org/10.55524/ijircst.2023.11.2.11","pdf_url":"http://dx.doi.org/10.55524/ijircst.2023.11.2.11","source":{"id":"https://openalex.org/S4210230306","display_name":"International Journal of Innovative Research in Computer Science & Technology","issn_l":"2347-5552","issn":["2347-5552"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Innovative Research in Computer Science and Technology","raw_type":"journal-article"},{"id":"pmh:oai:zenodo.org:7837321","doi":null,"is_oa":true,"landing_page_url":"https://zenodo.org/record/7837321","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"International Journal of Innovative Research in Computer Science & Technology (IJIRCST) 11(2) 58-61","raw_type":"info:eu-repo/semantics/article"},{"id":"doi:10.5281/zenodo.7837320","doi":"https://doi.org/10.5281/zenodo.7837320","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.7837320","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"JournalArticle"},{"id":"doi:10.5281/zenodo.7837321","doi":"https://doi.org/10.5281/zenodo.7837321","is_oa":true,"landing_page_url":"https://doi.org/10.5281/zenodo.7837321","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"JournalArticle"}],"best_oa_location":{"id":"doi:10.55524/ijircst.2023.11.2.11","doi":"https://doi.org/10.55524/ijircst.2023.11.2.11","is_oa":true,"landing_page_url":"https://doi.org/10.55524/ijircst.2023.11.2.11","pdf_url":"http://dx.doi.org/10.55524/ijircst.2023.11.2.11","source":{"id":"https://openalex.org/S4210230306","display_name":"International Journal of Innovative Research in Computer Science & Technology","issn_l":"2347-5552","issn":["2347-5552"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Innovative Research in Computer Science and Technology","raw_type":"journal-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4366265279.pdf","grobid_xml":"https://content.openalex.org/works/W4366265279.grobid-xml"},"referenced_works_count":4,"referenced_works":["https://openalex.org/W2409507433","https://openalex.org/W2527958550","https://openalex.org/W3121548865","https://openalex.org/W3199657899"],"related_works":["https://openalex.org/W4403724134","https://openalex.org/W3166111057","https://openalex.org/W3199657899","https://openalex.org/W4392771402","https://openalex.org/W2767078431","https://openalex.org/W7126022732","https://openalex.org/W3121548865","https://openalex.org/W4411208046","https://openalex.org/W2734443409","https://openalex.org/W3172574134"],"abstract_inverted_index":{"Design":[0],"Verification":[1,31],"in":[2,9,47,132,158],"VLSI":[3,159],"is":[4,32,78,96,102],"the":[5,10,19,24,29,33,38,43,48,52,70,73,81,155,163],"most":[6],"important":[7],"step":[8],"product":[11],"development":[12],"process.":[13],"It":[14],"aims":[15],"to":[16,69,110,116,144],"confirm":[17],"that":[18,58,76,101],"system":[20,40,71,86],"designed":[21,39],"meets":[22],"with":[23,80],"standards":[25],"and":[26,63,72,112,130,172,175,177,184],"requirements":[27],"of":[28,35,61,89,165],"system.":[30],"process":[34],"checking":[36],"whether":[37],"performs":[41],"all":[42],"required":[44],"functionality":[45],"specified":[46],"design":[49,77],"by":[50],"writing":[51],"test":[53],"bench":[54],"or":[55,139],"verification":[56,156],"environment":[57],"contains":[59],"group":[60],"classes":[62],"modules":[64],"which":[65,133],"generates":[66],"input":[67],"stimulus":[68],"output":[74],"from":[75],"compared":[79],"expected":[82],"output.":[83],"A":[84],"communication":[85,99,127],"has":[87,150,162],"set":[88],"roles":[90],"those":[91],"are":[92,108],"called":[93],"protocols.":[94],"UART":[95],"a":[97,145],"serial":[98],"protocol":[100],"used":[103,125,153],"when":[104],"only":[105],"two":[106],"devices":[107,138],"needed":[109],"communicate":[111],"it":[113,161],"uses":[114],"peer":[115,117],"topology.":[118],"I2C":[119],"stands":[120],"for":[121,126,154],"Inter":[122],"Integrated":[123],"Circuit":[124],"between":[128],"master":[129,146],"slave":[131,137],"more":[134],"than":[135],"one":[136],"memory":[140],"can":[141],"be":[142],"connected":[143],"device.":[147],"System":[148],"Verilog":[149,171],"been":[151],"primarily":[152],"purposes":[157],"because":[160],"features":[164],"Hardware":[166],"Description":[167],"Languages":[168],"such":[169],"as":[170],"VHDL,":[173],"C":[174],"C++":[176],"functional":[178],"coverage,":[179,181],"assertion":[180],"constrained":[182],"randomization":[183],"supports":[185],"OOPs":[186],"concepts.":[187]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1}],"updated_date":"2026-11-10T11:39:43.021295","created_date":"2023-04-20T00:00:00"}