{"id":"https://openalex.org/W4286571663","doi":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145","title":"Computing-in-Memory with SuperFlash\u00ae memBrain\u2122 Technology","display_name":"Computing-in-Memory with SuperFlash\u00ae memBrain\u2122 Technology","publication_year":2022,"publication_date":"2022-06-12","ids":{"openalex":"https://openalex.org/W4286571663","doi":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145"},"language":"en","primary_location":{"id":"doi:10.1109/vlsitechnologyandcir46769.2022.9830145","doi":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145","pdf_url":null,"source":{"id":"https://openalex.org/S4363605407","display_name":"IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103706358","display_name":"Nhan Do","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210093228","display_name":"Microchip Technology (United States)","ror":"https://ror.org/00kvz1558","country_code":"US","type":"company","lineage":["https://openalex.org/I4210093228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nhan Do","raw_affiliation_strings":["Microchip Technology, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microchip Technology, USA","institution_ids":["https://openalex.org/I4210093228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108920472","display_name":"Hieu V. Tran","orcid":"https://orcid.org/0009-0008-9815-1638","observed_orcids":["https://orcid.org/0009-0008-9815-1638"]},"institutions":[{"id":"https://openalex.org/I4210093228","display_name":"Microchip Technology (United States)","ror":"https://ror.org/00kvz1558","country_code":"US","type":"company","lineage":["https://openalex.org/I4210093228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hieu Tran","raw_affiliation_strings":["Microchip Technology, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microchip Technology, USA","institution_ids":["https://openalex.org/I4210093228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063099846","display_name":"Mark Reiten","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210093228","display_name":"Microchip Technology (United States)","ror":"https://ror.org/00kvz1558","country_code":"US","type":"company","lineage":["https://openalex.org/I4210093228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Reiten","raw_affiliation_strings":["Microchip Technology, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microchip Technology, USA","institution_ids":["https://openalex.org/I4210093228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210093228"],"apc_list":null,"apc_paid":null,"fwci":1.5542,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.78013391,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"238","last_page":"239"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/in-memory-computing","display_name":"in-memory computing","score":0.9660000205039978},{"id":"https://openalex.org/keywords/neuromorphic-memory","display_name":"neuromorphic memory","score":0.9290000200271606},{"id":"https://openalex.org/keywords/weight-tuning","display_name":"weight tuning","score":0.8799999952316284},{"id":"https://openalex.org/keywords/28-nm-technology","display_name":"28 nm technology","score":0.8519999980926514}],"concepts":[{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.862064003944397},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7497023940086365},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.4915357530117035},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.48548486828804016},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.44874897599220276},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43739187717437744},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43199414014816284},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4121701121330261},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3671838641166687},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.33315229415893555},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33024418354034424},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.21219441294670105},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13466942310333252},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11424154043197632},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/vlsitechnologyandcir46769.2022.9830145","doi":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145","is_oa":false,"landing_page_url":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830145","pdf_url":null,"source":{"id":"https://openalex.org/S4363605407","display_name":"IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1798990620","https://openalex.org/W2087582976","https://openalex.org/W2623060708","https://openalex.org/W2785784536","https://openalex.org/W2913255358"],"related_works":["https://openalex.org/W4407699823","https://openalex.org/W2940429698","https://openalex.org/W2785784536","https://openalex.org/W4415235867","https://openalex.org/W3033826949","https://openalex.org/W3088872754","https://openalex.org/W3090869401","https://openalex.org/W2914795752","https://openalex.org/W4200037397","https://openalex.org/W3114433235"],"abstract_inverted_index":{"The":[0,24],"concept":[1],"and":[2,56],"experimental":[3],"result":[4],"of":[5,26],"using":[6],"SuperFlash\u00ae":[7,42],"based":[8],"neuromorphic":[9],"memory":[10,29],"to":[11],"solve":[12],"the":[13],"data":[14],"communication":[15],"bottlenecks":[16],"in":[17,38,61],"neural":[18],"network":[19],"edge":[20],"devices":[21],"are":[22,58],"discussed.":[23],"implementation":[25],"a":[27,39],"2Mb":[28],"array":[30],"as":[31],"an":[32],"analog":[33],"vector":[34],"matrix":[35],"multiplier":[36],"(VMM)":[37],"28":[40],"nm":[41],"eFlash":[43],"(ESF3-28":[44],"nm)":[45],"process":[46],"together":[47],"with":[48],"design":[49],"concepts,":[50],"weight":[51],"tuning":[52],"technique,":[53],"performance":[54],"factors,":[55],"reliability,":[57],"also":[59],"presented":[60],"detail.":[62]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2023,"cited_by_count":1}],"updated_date":"2026-10-30T12:39:25.321706","created_date":"2022-07-22T00:00:00"}