{"id":"https://openalex.org/W4285113201","doi":"https://doi.org/10.1109/tpds.2022.3189390","title":"HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing","display_name":"HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing","publication_year":2022,"publication_date":"2022-07-08","ids":{"openalex":"https://openalex.org/W4285113201","doi":"https://doi.org/10.1109/tpds.2022.3189390"},"language":"en","primary_location":{"id":"doi:10.1109/tpds.2022.3189390","doi":"https://doi.org/10.1109/tpds.2022.3189390","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2022.3189390","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-a","cwts-core","dongbi-a","jufo-2","norway-2","poland-140","russia-white-list-1","vabb-shw"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["arxiv","crossref","datacite"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://arxiv.org/pdf/2201.03861","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051253991","display_name":"Andreas Kurth","orcid":"https://orcid.org/0000-0001-5613-9544","observed_orcids":["https://orcid.org/0000-0001-5613-9544"]},"institutions":[{"id":"https://openalex.org/I4405253860","display_name":"Integrated Systems Laboratory","ror":"https://ror.org/015f9wa43","country_code":"CH","type":"facility","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088","https://openalex.org/I4405253860"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Andreas Kurth","raw_affiliation_strings":["Integrated Systems Laboratory, Zurich, Switzerland"],"raw_orcid":"https://orcid.org/0000-0001-5613-9544","affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, Zurich, Switzerland","institution_ids":["https://openalex.org/I4405253860"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035314320","display_name":"Bj\u00f6rn Forsberg","orcid":"https://orcid.org/0000-0001-5994-7336","observed_orcids":["https://orcid.org/0000-0001-5994-7336"]},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Bj\u00f6rn Forsberg","raw_affiliation_strings":["D-ITET, Eidgenossische Technische Hochschule Zurich Departement Informationstechnologie und Elektrotechnik, Zurich, Switzerland"],"raw_orcid":"https://orcid.org/0000-0001-5994-7336","affiliations":[{"raw_affiliation_string":"D-ITET, Eidgenossische Technische Hochschule Zurich Departement Informationstechnologie und Elektrotechnik, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003234972","display_name":"L. Benini","orcid":"https://orcid.org/0000-0001-8068-3806","observed_orcids":["https://orcid.org/0000-0001-8068-3806","https://orcid.org/0000-0003-2785-8296"]},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Benini","raw_affiliation_strings":["DEIS, University of Bologna, Bologna, BO, Italy"],"raw_orcid":"https://orcid.org/0000-0001-8068-3806","affiliations":[{"raw_affiliation_string":"DEIS, University of Bologna, Bologna, BO, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2195,"currency":"USD","value_usd":2195},"apc_paid":null,"fwci":3.6483,"has_fulltext":true,"cited_by_count":25,"citation_normalized_percentile":{"value":0.94025486,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":93,"max":99},"biblio":{"volume":"33","issue":"12","first_page":"4368","last_page":"4382"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9682999849319458,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9682999849319458,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.02889999933540821,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.00139999995008111,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/heterogeneous-computing","display_name":"heterogeneous computing","score":0.9380000233650208},{"id":"https://openalex.org/keywords/network-on-chip","display_name":"network-on-chip","score":0.8140000104904175},{"id":"https://openalex.org/keywords/llvm","display_name":"LLVM","score":0.6809999942779541},{"id":"https://openalex.org/keywords/loop-tiling","display_name":"loop tiling","score":0.8339999914169312},{"id":"https://openalex.org/keywords/simulation-accuracy","display_name":"simulation accuracy","score":0.3050000071525574}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9075131416320801},{"id":"https://openalex.org/C2777062904","wikidata":"https://www.wikidata.org/wiki/Q545406","display_name":"Toolchain","level":3,"score":0.8635143041610718},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7167389392852783},{"id":"https://openalex.org/C172430144","wikidata":"https://www.wikidata.org/wiki/Q17111997","display_name":"Symmetric multiprocessor system","level":2,"score":0.6249793171882629},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.6136795282363892},{"id":"https://openalex.org/C126831891","wikidata":"https://www.wikidata.org/wiki/Q221673","display_name":"Host (biology)","level":2,"score":0.5522381067276001},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.550655722618103},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5258342027664185},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.520304262638092},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.41406798362731934},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4125814735889435},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34549248218536377},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.34209832549095154},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tpds.2022.3189390","doi":"https://doi.org/10.1109/tpds.2022.3189390","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tpds.2022.3189390","pdf_url":null,"source":{"id":"https://openalex.org/S97130795","display_name":"IEEE Transactions on Parallel and Distributed Systems","issn_l":"1045-9219","issn":["1045-9219","1558-2183","2161-9883"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["ccf-a","cwts-core","dongbi-a","jufo-2","norway-2","poland-140","russia-white-list-1","vabb-shw"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Parallel and Distributed Systems","raw_type":"journal-article"},{"id":"pmh:oai:arXiv.org:2201.03861","doi":null,"is_oa":true,"landing_page_url":"http://arxiv.org/abs/2201.03861","pdf_url":"https://arxiv.org/pdf/2201.03861","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},{"id":"pmh:oai:cris.unibo.it:11585/904934","doi":null,"is_oa":false,"landing_page_url":"https://hdl.handle.net/11585/904934","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},{"id":"doi:10.48550/arxiv.2201.03861","doi":"https://doi.org/10.48550/arxiv.2201.03861","is_oa":true,"landing_page_url":"https://doi.org/10.48550/arxiv.2201.03861","pdf_url":null,"source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Preprint"}],"best_oa_location":{"id":"pmh:oai:arXiv.org:2201.03861","doi":null,"is_oa":true,"landing_page_url":"http://arxiv.org/abs/2201.03861","pdf_url":"https://arxiv.org/pdf/2201.03861","source":{"id":"https://openalex.org/S4306400194","display_name":"arXiv (Cornell University)","issn_l":"2331-8422","issn":["2331-8422"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I205783295","host_organization_name":"Cornell University","host_organization_lineage":["https://openalex.org/I205783295"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"text"},"sustainable_development_goals":[],"study_designs":[],"awards":[{"id":"https://openalex.org/G3930056189","display_name":null,"funder_award_id":"877056","funder_id":"https://openalex.org/F4320327207","funder_display_name":"Electronic Components and Systems for European Leadership"}],"funders":[{"id":"https://openalex.org/F4320327207","display_name":"Electronic Components and Systems for European Leadership","ror":"https://ror.org/02afwgc64"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W4285113201.pdf","grobid_xml":"https://content.openalex.org/works/W4285113201.grobid-xml"},"referenced_works_count":55,"referenced_works":["https://openalex.org/W162127356","https://openalex.org/W1483870316","https://openalex.org/W1523401229","https://openalex.org/W1579685561","https://openalex.org/W1864199185","https://openalex.org/W1999085092","https://openalex.org/W2021124483","https://openalex.org/W2023187357","https://openalex.org/W2072916763","https://openalex.org/W2102976251","https://openalex.org/W2103742924","https://openalex.org/W2106562406","https://openalex.org/W2128120785","https://openalex.org/W2135218079","https://openalex.org/W2318354022","https://openalex.org/W2337148482","https://openalex.org/W2418145342","https://openalex.org/W2507785513","https://openalex.org/W2560221416","https://openalex.org/W2583280147","https://openalex.org/W2744562207","https://openalex.org/W2759541633","https://openalex.org/W2763302904","https://openalex.org/W2845210056","https://openalex.org/W2884267664","https://openalex.org/W2889340368","https://openalex.org/W2912012512","https://openalex.org/W2921494082","https://openalex.org/W2922398414","https://openalex.org/W2936567838","https://openalex.org/W2946072469","https://openalex.org/W2964170821","https://openalex.org/W2982135357","https://openalex.org/W2998228662","https://openalex.org/W3007888060","https://openalex.org/W3011470274","https://openalex.org/W3011801493","https://openalex.org/W3013692244","https://openalex.org/W3016849989","https://openalex.org/W3027968530","https://openalex.org/W3029622172","https://openalex.org/W3032789745","https://openalex.org/W3036079062","https://openalex.org/W3039606915","https://openalex.org/W3048854702","https://openalex.org/W3081627712","https://openalex.org/W3082020764","https://openalex.org/W3085021637","https://openalex.org/W3091524708","https://openalex.org/W3122737223","https://openalex.org/W3153263805","https://openalex.org/W3154811273","https://openalex.org/W3199375732","https://openalex.org/W4233649229","https://openalex.org/W4242503252"],"related_works":["https://openalex.org/W2964170821","https://openalex.org/W4389544721","https://openalex.org/W4406014807","https://openalex.org/W4309152378","https://openalex.org/W2528431790","https://openalex.org/W1665373133","https://openalex.org/W7061354654","https://openalex.org/W2132078224","https://openalex.org/W6885147878","https://openalex.org/W2906737788"],"abstract_inverted_index":{"Heterogeneous":[0],"computers":[1,79],"integrate":[2],"general-purpose":[3],"host":[4,97,107],"processors":[5],"with":[6,12,51,114],"domain-specific":[7],"accelerators":[8,82,111],"to":[9,33,44,101,151,181,188,193,197],"combine":[10],"versatility":[11],"efficiency":[13],"and":[14,28,38,57,74,90,109,112,125,147,161,177,182,201],"high":[15],"performance.":[16],"To":[17],"realize":[18],"the":[19,142,164,172,184,198],"full":[20,165],"potential":[21],"of":[22,77,81,86,167,191],"heterogeneous":[23,46,78,122,129,168],"computers,":[24,47],"however,":[25],"many":[26],"hardware":[27],"software":[29],"design":[30],"challenges":[31],"have":[32],"be":[34,42],"overcome.":[35],"While":[36],"architectural":[37],"system":[39,148],"simulators":[40],"can":[41,174],"used":[43],"analyze":[45],"they":[48],"are":[49],"faced":[50],"unavoidable":[52],"compromises":[53],"between":[54,105],"simulation":[55],"speed":[56],"performance":[58],"modeling":[59],"accuracy.":[60],"In":[61],"this":[62],"work":[63],"we":[64],"present":[65],"HEROv2,":[66],"an":[67,91],"FPGA-based":[68],"research":[69,160],"platform":[70],"that":[71],"enables":[72,158],"accurate":[73],"fast":[75],"exploration":[76],"consisting":[80],"based":[83,131],"on":[84,132,163],"clusters":[85],"32-bit":[87,110],"RISC-V":[88],"cores":[89],"application-class":[92],"64-bit":[93,106],"ARMv8":[94],"or":[95],"RV64":[96],"processor.":[98],"HEROv2":[99,136,157],"allows":[100],"seamlessly":[102],"share":[103],"data":[104,179],"s":[108],"comes":[113],"a":[115,120,126,189,210],"fully":[116],"open-source":[117],"on-chip":[118],"network,":[119],"unified":[121],"programming":[123],"interface,":[124],"mixed-data-model,":[127],"mixed-ISA":[128],"compiler":[130,173],"LLVM.":[133],"We":[134,154],"evaluate":[135],"in":[137,202],"four":[138],"case":[139],"studies":[140],"from":[141,183],"application":[143],"level":[144],"over":[145],"toolchain":[146],"architecture":[149],"down":[150],"accelerator":[152],"microarchitecture.":[153],"demonstrate":[155],"how":[156],"effective":[159],"development":[162],"stack":[166],"computing.":[169],"For":[170],"instance,":[171],"tile":[175],"loops":[176],"infer":[178],"transfers":[180],"accelerators,":[185],"which":[186,213],"leads":[187],"speedup":[190],"up":[192],"4.4":[194],"\u00d7":[195,216],"compared":[196],"original":[199],"program":[200],"most":[203],"cases":[204],"is":[205],"only":[206],"15%":[207],"slower":[208],"than":[209],"handwritten":[211],"implementation,":[212],"requires":[214],"2.6":[215],"more":[217],"code.":[218]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":8},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":2}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2022-07-14T00:00:00"}
