{"id":"https://openalex.org/W4240814530","doi":"https://doi.org/10.1109/mmsp.1997.602673","title":"An algorithm-hardware-system approach to VLIW multimedia processors","display_name":"An algorithm-hardware-system approach to VLIW multimedia processors","publication_year":2002,"publication_date":"2002-11-22","ids":{"openalex":"https://openalex.org/W4240814530","doi":"https://doi.org/10.1109/mmsp.1997.602673"},"language":"en","primary_location":{"id":"doi:10.1109/mmsp.1997.602673","doi":"https://doi.org/10.1109/mmsp.1997.602673","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mmsp.1997.602673","pdf_url":null,"source":{"id":"https://openalex.org/S4363605768","display_name":"IEEE International Workshop on Multimedia Signal Processing (MMSP)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of First Signal Processing Society Workshop on Multimedia Signal Processing","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049023356","display_name":"Johannes Kneip","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J. Kneip","raw_affiliation_strings":["Laboratory f\u00fcr Informations technologie, Universit\u00e4t Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory f\u00fcr Informations technologie, Universit\u00e4t Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039777488","display_name":"Mladen Berekovi\u0107","orcid":"https://orcid.org/0000-0003-1911-756X","observed_orcids":["https://orcid.org/0000-0003-1911-756X"]},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Berekovic","raw_affiliation_strings":["Laboratory f\u00fcr Informations technologie, Universit\u00e4t Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory f\u00fcr Informations technologie, Universit\u00e4t Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050808949","display_name":"P. Pirsch","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"P. Pirsch","raw_affiliation_strings":["Laboratory f\u00fcr Informations technologie, Universit\u00e4t Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Laboratory f\u00fcr Informations technologie, Universit\u00e4t Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I114112103"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.31434051,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"11","issue":null,"first_page":"433","last_page":"438"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8148999810218811,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8148999810218811,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.1785999983549118,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0019000000320374966,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vliw-architecture","display_name":"VLIW architecture","score":0.8519999980926514},{"id":"https://openalex.org/keywords/multimedia-processors","display_name":"multimedia processors","score":0.9290000200271606},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"instruction-level parallelism","score":0.8629999756813049},{"id":"https://openalex.org/keywords/degree-of-parallelism","display_name":"degree of parallelism","score":0.8420000076293945},{"id":"https://openalex.org/keywords/vlsi-design","display_name":"VLSI design","score":0.9829999804496765},{"id":"https://openalex.org/keywords/compilers","display_name":"compilers","score":0.7580000162124634},{"id":"https://openalex.org/keywords/dsp-processors","display_name":"DSP processors","score":0.46700000762939453},{"id":"https://openalex.org/keywords/processor-efficiency","display_name":"processor efficiency","score":0.36000001430511475}],"concepts":[{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.9563252925872803},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8873670101165771},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7054882645606995},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.6548910737037659},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.5682125091552734},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5439467430114746},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5283297300338745},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4995250701904297},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4919905364513397},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2609371542930603},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19129547476768494},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mmsp.1997.602673","doi":"https://doi.org/10.1109/mmsp.1997.602673","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mmsp.1997.602673","pdf_url":null,"source":{"id":"https://openalex.org/S4363605768","display_name":"IEEE International Workshop on Multimedia Signal Processing (MMSP)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of First Signal Processing Society Workshop on Multimedia Signal Processing","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1733053777","https://openalex.org/W1984972320","https://openalex.org/W2042738477","https://openalex.org/W2120230074","https://openalex.org/W2541922288","https://openalex.org/W4233091208","https://openalex.org/W6729152395"],"related_works":["https://openalex.org/W1571734682","https://openalex.org/W7097613791","https://openalex.org/W2000139719","https://openalex.org/W1587025594","https://openalex.org/W2006020173","https://openalex.org/W2035591286","https://openalex.org/W2703495671","https://openalex.org/W135117436","https://openalex.org/W2160017214","https://openalex.org/W2023132668"],"abstract_inverted_index":{"A":[0],"number":[1],"of":[2,39,49,81],"recently":[3],"published":[4],"DSPs":[5],"and":[6,22,61,71],"multimedia":[7,29],"processors":[8],"emphasize":[9],"on":[10],"Very":[11],"Long":[12],"Instruction":[13],"Word":[14],"(VLIW)":[15],"architectures":[16],"to":[17,74],"achieve":[18],"flexibility,":[19],"processing":[20],"power":[21],"high-level":[23],"language":[24],"programmability":[25],"needed":[26],"for":[27],"future":[28],"applications.":[30],"In":[31],"this":[32],"paper":[33],"we":[34],"show":[35],"that":[36],"exclusive":[37],"exploitation":[38],"instruction":[40],"level":[41],"parallelism":[42,50],"decreases":[43],"in":[44],"efficiency":[45],"as":[46],"the":[47],"degree":[48],"increases.":[51],"This":[52],"is":[53],"mainly":[54],"caused":[55],"by":[56],"algorithm":[57],"characteristics,":[58],"VLSI":[59],"design":[60],"compiler":[62],"restrictions.":[63],"We":[64],"discuss":[65],"selected":[66],"aspects":[67],"from":[68,77],"these":[69],"fields":[70],"possible":[72],"solutions":[73],"upcoming":[75],"bottlenecks":[76],"a":[78],"practical":[79],"point":[80],"view.":[82]},"counts_by_year":[],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2022-05-12T00:00:00"}