{"id":"https://openalex.org/W4240479181","doi":"https://doi.org/10.1109/ishls.1994.302337","title":"Code generation for a DSP processor","display_name":"Code generation for a DSP processor","publication_year":2002,"publication_date":"2002-12-17","ids":{"openalex":"https://openalex.org/W4240479181","doi":"https://doi.org/10.1109/ishls.1994.302337"},"language":"en","primary_location":{"id":"doi:10.1109/ishls.1994.302337","doi":"https://doi.org/10.1109/ishls.1994.302337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ishls.1994.302337","pdf_url":null,"source":{"id":"https://openalex.org/S7407119841","display_name":"International Symposium on High-Level Synthesis (ISSS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 7th International Symposium on High-Level Synthesis","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054845461","display_name":"Wei\u2010Kai Cheng","orcid":"https://orcid.org/0000-0002-2867-6200","observed_orcids":["https://orcid.org/0000-0002-2867-6200"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Wei-Kai Cheng","raw_affiliation_strings":["Department of Computer Science, Tsinghua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Tsinghua University, Hsinchu, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071624937","display_name":"Youn-Long Lin","orcid":"https://orcid.org/0000-0002-4106-8082","observed_orcids":["https://orcid.org/0000-0002-4106-8082"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Youn-Long Lin","raw_affiliation_strings":["Department of Computer Science, Tsinghua University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Tsinghua University, Hsinchu, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4025,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.50929253,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"82","last_page":"87"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9448000192642212,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9448000192642212,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.050700001418590546,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.0010000000474974513,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/microcode-generation","display_name":"microcode generation","score":0.8100000023841858},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"high-level synthesis","score":0.8040000200271606},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"instruction scheduling","score":0.746999979019165},{"id":"https://openalex.org/keywords/register-allocation","display_name":"register allocation","score":0.9670000076293945},{"id":"https://openalex.org/keywords/memory-access-conflicts","display_name":"memory access conflicts","score":0.8259999752044678},{"id":"https://openalex.org/keywords/parallel-architectures","display_name":"parallel computing architecture","score":0.8100000023841858}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.829889178276062},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.7788013219833374},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.586250364780426},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.5589345693588257},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5141892433166504},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.47695887088775635},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4595780074596405},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.44683319330215454},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4413837790489197},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42767634987831116},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3483753204345703},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.29458147287368774},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.23936253786087036},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.20820221304893494},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20370319485664368},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15115338563919067},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.11292266845703125},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.1057528555393219},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ishls.1994.302337","doi":"https://doi.org/10.1109/ishls.1994.302337","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ishls.1994.302337","pdf_url":null,"source":{"id":"https://openalex.org/S7407119841","display_name":"International Symposium on High-Level Synthesis (ISSS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 7th International Symposium on High-Level Synthesis","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1835230495","https://openalex.org/W1993997195","https://openalex.org/W2074537610","https://openalex.org/W2093032919","https://openalex.org/W2093842169","https://openalex.org/W2110134206","https://openalex.org/W2155314350","https://openalex.org/W3146011930","https://openalex.org/W4206153422","https://openalex.org/W4211015501","https://openalex.org/W4243808412"],"related_works":["https://openalex.org/W2043381627","https://openalex.org/W1590803656","https://openalex.org/W2103837157","https://openalex.org/W7100364941","https://openalex.org/W2144402443","https://openalex.org/W1999421209","https://openalex.org/W7099944215","https://openalex.org/W2168039487","https://openalex.org/W2527385298","https://openalex.org/W2146337913"],"abstract_inverted_index":{"Proposes":[0],"a":[1,11,31,52,91,126],"method":[2],"for":[3,47,102],"compiling":[4],"an":[5,75],"application":[6],"program":[7],"into":[8,90,105],"microcodes":[9],"of":[10,23,128,132],"programmable":[12],"DSP":[13,18,53,142],"processor.":[14],"Since":[15],"most":[16],"state-of-the-art":[17],"processors":[19],"feature":[20],"some":[21],"sort":[22],"parallel":[24],"processing":[25],"architectures,":[26],"the":[27,44,59,69,81,95,139,146],"code":[28,54],"generation":[29],"is":[30,149],"non-trivial":[32],"task.":[33],"Based":[34],"on":[35],"several":[36],"scheduling":[37,88],"and":[38,62,100,110,123],"allocation":[39],"techniques":[40],"previously":[41],"developed":[42],"by":[43],"CAD":[45],"community":[46],"high-level":[48],"synthesis,":[49],"we":[50,84],"propose":[51],"generator.":[55],"We":[56],"emphasize":[57],"reducing":[58],"memory":[60,108],"access":[61,109],"register":[63,111],"usage":[64,112],"conflicts,":[65],"which":[66,135],"often":[67],"lengthen":[68],"total":[70],"execution":[71],"time.":[72],"Starting":[73],"with":[74],"as-soon-as-possible":[76],"scheduling,":[77],"without":[78],"regard":[79],"to":[80],"resource":[82],"constraints,":[83],"transform":[85],"this":[86],"illegal":[87],"step-by-step":[89],"legal":[92],"one.":[93],"In":[94],"meantime,":[96],"registers":[97],"are":[98,136],"allocated":[99],"reallocated":[101],"variables,":[103],"taking":[104],"account":[106],"both":[107],"constraints.":[113],"A":[114],"software":[115],"system":[116],"called":[117],"THEDA.DSP/sub":[118],"CG/":[119],"has":[120],"been":[121],"implemented":[122],"tested":[124],"using":[125],"set":[127],"benchmark":[129],"programs.":[130],"Simulation":[131],"generated":[133],"codes":[134],"targeted":[137],"towards":[138],"TI":[140],"TMS320C40":[141],"processor":[143],"shows":[144],"that":[145],"proposed":[147],"approach":[148],"indeed":[150],"very":[151],"effective.>":[152]},"counts_by_year":[],"updated_date":"2026-10-28T10:33:24.094632","created_date":"2022-05-12T00:00:00"}