{"id":"https://openalex.org/W4234585396","doi":"https://doi.org/10.7873/date.2013.294","title":"Formal Verification of Analog Circuit Parameters across Variation Utilizing SAT","display_name":"Formal Verification of Analog Circuit Parameters across Variation Utilizing SAT","publication_year":2013,"publication_date":"2013-01-01","ids":{"openalex":"https://openalex.org/W4234585396","doi":"https://doi.org/10.7873/date.2013.294"},"language":"en","primary_location":{"id":"doi:10.7873/date.2013.294","doi":"https://doi.org/10.7873/date.2013.294","is_oa":false,"landing_page_url":"https://doi.org/10.7873/date.2013.294","pdf_url":null,"source":{"id":"https://openalex.org/S4306418181","display_name":"Design, Automation, and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041511489","display_name":"Merritt P. Miller","orcid":"https://orcid.org/0000-0003-2170-2549","observed_orcids":["https://orcid.org/0000-0003-2170-2549"]},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Merritt Miller","raw_affiliation_strings":["Department of Electrical and Computer Engineering UCSB"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering UCSB","institution_ids":["https://openalex.org/I154570441"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026518797","display_name":"Forrest D. Brewer","orcid":"https://orcid.org/0000-0002-3076-9297","observed_orcids":["https://orcid.org/0000-0002-3076-9297"]},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Forrest Brewer","raw_affiliation_strings":["Department of Electrical and Computer Engineering UCSB"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering UCSB","institution_ids":["https://openalex.org/I154570441"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I154570441"],"apc_list":null,"apc_paid":null,"fwci":0.6325,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.64401239,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1442","last_page":"1447"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.7451000213623047,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.7451000213623047,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.1712999939918518,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.019899999722838402,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/analog-circuit-verification","display_name":"analog circuit verification","score":0.8849999904632568},{"id":"https://openalex.org/keywords/sat-based-verification","display_name":"SAT-based verification","score":0.6489999890327454},{"id":"https://openalex.org/keywords/circuit-parameter-variation","display_name":"circuit parameter variation","score":0.6600000262260437},{"id":"https://openalex.org/keywords/analog-circuit-design","display_name":"analog circuit design","score":0.47699999809265137}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6869427561759949},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.5095558166503906},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.47647640109062195},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4576607346534729},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.45250260829925537},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.42538541555404663},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4192520081996918},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.41378480195999146},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4118746221065521},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.40890198945999146},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3588200509548187},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.32512974739074707},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19276437163352966},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17354929447174072},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15677139163017273},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11369660496711731},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11272439360618591},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07268384099006653},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.7873/date.2013.294","doi":"https://doi.org/10.7873/date.2013.294","is_oa":false,"landing_page_url":"https://doi.org/10.7873/date.2013.294","pdf_url":null,"source":{"id":"https://openalex.org/S4306418181","display_name":"Design, Automation, and Test in Europe","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2888592213","https://openalex.org/W7203477767","https://openalex.org/W4242542680","https://openalex.org/W2153160343","https://openalex.org/W3143982981","https://openalex.org/W2158533859","https://openalex.org/W7099945432","https://openalex.org/W7099324083","https://openalex.org/W189254549","https://openalex.org/W2635078874"],"abstract_inverted_index":{"A":[0],"fast":[1],"technique":[2,16],"for":[3],"proving":[4],"steady-state":[5],"analog":[6],"circuit":[7,21],"operation":[8],"constraints":[9],"is":[10,17,48],"described.":[11],"Based":[12],"on":[13],"SAT,":[14],"the":[15,35],"applicable":[18],"to":[19],"practical":[20],"design":[22],"and":[23,44],"modeling":[24],"scenarios":[25],"as":[26],"it":[27],"does":[28],"not":[29],"require":[30],"algebraic":[31],"device":[32],"models.":[33],"Despite":[34],"complexity":[36],"of":[37],"representing":[38],"accurate":[39],"transistor":[40],"I/V":[41],"characteristics,":[42],"run-time":[43],"problem":[45],"scaling":[46],"behavior":[47],"excellent.":[49]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2022-05-12T00:00:00"}