{"id":"https://openalex.org/W4231486519","doi":"https://doi.org/10.1109/ieeestd.2013.6515989","title":"IEEE Standard for Test Access Port and Boundary-Scan Architecture","display_name":"IEEE Standard for Test Access Port and Boundary-Scan Architecture","publication_year":2013,"publication_date":"2013-02-06","ids":{"openalex":"https://openalex.org/W4231486519","doi":"https://doi.org/10.1109/ieeestd.2013.6515989"},"language":"en","primary_location":{"id":"doi:10.1109/ieeestd.2013.6515989","doi":"https://doi.org/10.1109/ieeestd.2013.6515989","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ieeestd.2013.6515989","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":null,"raw_type":"standard"},"volume":null,"type":"standard","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":246,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.005200000014156103,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/test-access-port","display_name":"test access port","score":0.906000018119812},{"id":"https://openalex.org/keywords/boundary-scan","display_name":"boundary scan","score":0.8050000071525574},{"id":"https://openalex.org/keywords/ieee-1149-1","display_name":"IEEE 1149.1","score":0.8519999980926514},{"id":"https://openalex.org/keywords/printed-circuit-board-testing","display_name":"printed circuit board testing","score":0.9259999990463257},{"id":"https://openalex.org/keywords/test-instructions","display_name":"test instructions","score":0.5550000071525574},{"id":"https://openalex.org/keywords/test-language","display_name":"test language","score":0.5410000085830688}],"concepts":[{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5959445238113403},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.5570474863052368},{"id":"https://openalex.org/C992767","wikidata":"https://www.wikidata.org/wiki/Q895156","display_name":"Boundary scan","level":3,"score":0.556523859500885},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.5496503114700317},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5120077729225159},{"id":"https://openalex.org/C62354387","wikidata":"https://www.wikidata.org/wiki/Q875399","display_name":"Boundary (topology)","level":2,"score":0.45682385563850403},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.37810808420181274},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2423611283302307},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.21515017747879028},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21032121777534485},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1674041748046875},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.11544212698936462},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11489608883857727},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.05367043614387512},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ieeestd.2013.6515989","doi":"https://doi.org/10.1109/ieeestd.2013.6515989","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ieeestd.2013.6515989","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":null,"raw_type":"standard"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4241024413","https://openalex.org/W7098638674","https://openalex.org/W2100739104","https://openalex.org/W2019148511","https://openalex.org/W2418496246","https://openalex.org/W1561952310","https://openalex.org/W2168273362","https://openalex.org/W2108172359","https://openalex.org/W326924995","https://openalex.org/W2113280124"],"abstract_inverted_index":{"Circuitry":[0],"that":[1,56,84,103],"may":[2,113],"be":[3,114],"built":[4],"into":[5],"an":[6],"integrated":[7],"circuit":[8,20,77],"to":[9,61,63,70],"assist":[10,71],"in":[11],"the":[12,23,57,90,110],"test,":[13],"maintenance":[14],"and":[15,22,39,97],"support":[16],"of":[17,25,46,67,74,89,93,108],"assembled":[18,75],"printed":[19,76],"boards":[21],"test":[24,40,47],"internal":[26],"circuits":[27],"is":[28,49,59,82,101],"defined.":[29],"The":[30],"circuitry":[31],"includes":[32],"a":[33,52,64,80,98],"standard":[34],"interface":[35],"through":[36],"which":[37],"instructions":[38,68],"data":[41],"are":[42],"communicated.":[43],"A":[44],"set":[45,66],"features":[48,112],"defined,":[50],"including":[51],"boundary-scan":[53],"register,":[54],"such":[55,94],"component":[58],"able":[60],"respond":[62],"minimum":[65],"designed":[69],"with":[72],"testing":[73],"boards.":[78],"Also,":[79],"language":[81,100],"defined":[83,102],"allows":[85,104],"rigorous":[86,105],"structural":[87],"description":[88,107],"component-specific":[91],"aspects":[92],"testability":[95,111],"features,":[96],"second":[99],"procedural":[106],"how":[109],"used.":[115]},"counts_by_year":[{"year":2026,"cited_by_count":7},{"year":2025,"cited_by_count":6},{"year":2024,"cited_by_count":17},{"year":2023,"cited_by_count":14},{"year":2022,"cited_by_count":15},{"year":2021,"cited_by_count":10},{"year":2020,"cited_by_count":11},{"year":2019,"cited_by_count":9},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":9},{"year":2015,"cited_by_count":15},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":6}],"updated_date":"2026-10-29T09:56:32.521200","created_date":"2022-05-12T00:00:00"}