{"id":"https://openalex.org/W4214915417","doi":null,"title":"Code Transformations to Improve Memory Parallelism","display_name":"Code Transformations to Improve Memory Parallelism","publication_year":null,"publication_date":null,"ids":{"openalex":"https://openalex.org/W4214915417"},"language":"en","primary_location":{"id":"pmh:oai:CiteSeerX.psu:10.1.1.415.6319","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.415.6319","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~amza/ece1747h/papers/pai_micro99.pdf","raw_type":"text"},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110871804","display_name":"Vijay S. Pai","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I74775410","display_name":"Rice University","ror":"https://ror.org/008zs3103","country_code":"US","type":"education","lineage":["https://openalex.org/I74775410"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vijay S. Paiy","raw_affiliation_strings":["Electrical and Computer Engineering, Rice University, Houston, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Rice University, Houston, TX, USA","institution_ids":["https://openalex.org/I74775410"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Sarita Advez Yelectrical","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]},{"id":"https://openalex.org/I2801919071","display_name":"University of Illinois System","ror":"https://ror.org/05e94g991","country_code":"US","type":"education","lineage":["https://openalex.org/I2801919071"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sarita Advez Yelectrical","raw_affiliation_strings":["Computer Science, University of Illinois, Urbana, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science, University of Illinois, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225","https://openalex.org/I2801919071"]}]},{"author_position":"last","author":{"id":null,"display_name":"Computer Engineering","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Computer Engineering","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.0,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/program-transformation","display_name":"program transformation","score":0.7369999885559082},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"instruction-level parallelism","score":0.875},{"id":"https://openalex.org/keywords/cache-locality","display_name":"cache locality","score":0.7319999933242798},{"id":"https://openalex.org/keywords/compiler-optimization","display_name":"compiler optimization","score":0.6660000085830688},{"id":"https://openalex.org/keywords/multiprocessor-systems","display_name":"multiprocessor systems","score":0.7110000252723694}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8695827126502991},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7869893312454224},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.7435078620910645},{"id":"https://openalex.org/C3543717","wikidata":"https://www.wikidata.org/wiki/Q6007302","display_name":"Implicit parallelism","level":4,"score":0.6719891428947449},{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.6042267084121704},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5972913503646851},{"id":"https://openalex.org/C42992933","wikidata":"https://www.wikidata.org/wiki/Q691169","display_name":"Task parallelism","level":3,"score":0.48176074028015137},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.46458700299263},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.4560553729534149},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.42048200964927673},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.3587401807308197},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.276157021522522},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.2530437707901001},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1778755486011505},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"pmh:oai:CiteSeerX.psu:10.1.1.415.6319","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.415.6319","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.eecg.toronto.edu/~amza/ece1747h/papers/pai_micro99.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W346213406","https://openalex.org/W1964483599","https://openalex.org/W1966285605","https://openalex.org/W2044604658","https://openalex.org/W2045786690","https://openalex.org/W2077790567","https://openalex.org/W2078900897","https://openalex.org/W2105321788","https://openalex.org/W2107916517","https://openalex.org/W2119609467","https://openalex.org/W2138007781","https://openalex.org/W2145021036","https://openalex.org/W2146468199","https://openalex.org/W2151134402","https://openalex.org/W2168012066","https://openalex.org/W2207094710"],"related_works":["https://openalex.org/W1542975976","https://openalex.org/W2146468199","https://openalex.org/W1574791090","https://openalex.org/W2626653144","https://openalex.org/W2168012066","https://openalex.org/W2077960035","https://openalex.org/W7097842373","https://openalex.org/W2590238087","https://openalex.org/W1847216341","https://openalex.org/W2521125845"],"abstract_inverted_index":{"Current":[0],"microprocessors":[1],"incorporate":[2],"techniques":[3,17],"to":[4,56,72,114],"exploit":[5],"instruction-level":[6],"parallelism":[7,74],"(ILP).":[8],"However,":[9],"previous":[10],"work":[11,68],"has":[12],"shown":[13],"that":[14],"these":[15],"ILP":[16],"are":[18],"less":[19],"effective":[20],"in":[21,36,75,110,121,127],"removing":[22],"memory":[23,31,65,77,111],"stall":[24],"time":[25,116],"than":[26,39],"CPU":[27],"time,":[28],"making":[29],"the":[30,61,76,85],"system":[32,78],"a":[33,122,128,135],"greater":[34],"bottleneck":[35],"ILP-based":[37],"systems":[38],"previous-generation":[40],"systems.":[41],"These":[42],"deficiencies":[43],"arise":[44],"largely":[45],"because":[46],"applications":[47],"present":[48,94],"limited":[49],"opportunities":[50],"for":[51,101],"an":[52,95],"out-of-order":[53],"issue":[54],"processor":[55],"overlap":[57],"multiple":[58,81],"read":[59,82],"misses,":[60],"dominant":[62],"source":[63],"of":[64],"stalls.":[66],"This":[67],"proposes":[69],"code":[70],"transformations":[71],"increase":[73],"by":[79],"overlapping":[80],"misses":[83],"within":[84],"same":[86],"instruction":[87],"window,":[88],"while":[89],"preserving":[90],"cache":[91],"locality.":[92],"We":[93,130],"analysis":[96],"and":[97,124],"transformation":[98],"framework":[99],"suitable":[100],"compiler":[102],"implementation.":[103],"Our":[104],"simulation":[105],"experiments":[106],"show":[107],"substantial":[108],"increases":[109],"parallelism,":[112],"leading":[113],"execution":[115],"reductions":[117],"averaging":[118],"23":[119],"%":[120,126],"multiprocessor":[123],"30":[125],"uniprocessor.":[129],"see":[131],"similar":[132],"benefits":[133],"on":[134],"Convex":[136],"Exemplar.":[137],"1.":[138]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-11-12T12:28:57.059296","created_date":"2022-03-05T00:00:00"}