{"id":"https://openalex.org/W4072037","doi":null,"title":"Unifying FPGAs and SIMD Arrays","display_name":"Unifying FPGAs and SIMD Arrays","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W4072037","mag":"4072037"},"language":"en","primary_location":{"id":"pmh:oai:CiteSeerX.psu:10.1.1.182.5776","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.182.5776","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.seas.upenn.edu/%7Eandre/pdf/dpga_fpga94.pdf","raw_type":"text"},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084913764","display_name":"Michael Bolotski","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Bolotski Andr","raw_affiliation_strings":["Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074248757","display_name":"DeHon Thomas","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"DeHon Thomas","raw_affiliation_strings":["Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]},{"author_position":"last","author":{"id":null,"display_name":"F. K. Knight","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I63966007","display_name":"Massachusetts Institute of Technology","ror":"https://ror.org/042nb2s44","country_code":"US","type":"education","lineage":["https://openalex.org/I63966007"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"F. K. Knight","raw_affiliation_strings":["Massachusetts Institute of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Massachusetts Institute of Technology","institution_ids":["https://openalex.org/I63966007"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I63966007"],"apc_list":null,"apc_paid":null,"fwci":2.3967,"has_fulltext":false,"cited_by_count":35,"citation_normalized_percentile":{"value":0.85962692,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":95},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.5425000190734863,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.5425000190734863,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.32760000228881836,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.035999998450279236,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.9959999918937683}],"concepts":[{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.918041467666626},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7710347175598145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7405325174331665},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.6199731230735779},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6150822043418884},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.5229381322860718},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5203637480735779},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4884840250015259},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.48380011320114136},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.4597926139831543},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2949199080467224},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2894919514656067},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2655208110809326},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11654230952262878},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.08617112040519714},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"pmh:oai:CiteSeerX.psu:10.1.1.182.5776","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.182.5776","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.seas.upenn.edu/%7Eandre/pdf/dpga_fpga94.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.24.7951","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.24.7951","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.caltech.edu/research/ic/transit/transit-notes/tn95.ps.Z","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.79.97","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.79.97","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ecs.umass.edu/ece/tessier/courses/697ff/dpga-fpga94.pdf","raw_type":"text"},{"id":"mag:4072037","doi":null,"is_oa":false,"landing_page_url":"https://www.seas.upenn.edu/~andre/pdf/dpga_fpga1994.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W122745727","https://openalex.org/W301071703","https://openalex.org/W1979547397","https://openalex.org/W1987920560","https://openalex.org/W2006090396","https://openalex.org/W2108314268","https://openalex.org/W2121066557","https://openalex.org/W2152496451","https://openalex.org/W2152699447","https://openalex.org/W2158365276","https://openalex.org/W2538506363","https://openalex.org/W2589107639"],"related_works":["https://openalex.org/W7083333391","https://openalex.org/W3003711841","https://openalex.org/W2955366531","https://openalex.org/W7095647188","https://openalex.org/W2160008175","https://openalex.org/W2155034476","https://openalex.org/W52105682","https://openalex.org/W2188840553","https://openalex.org/W7097856553","https://openalex.org/W2601195074"],"abstract_inverted_index":{"Field-Programmable":[0],"Gate":[1,91],"Arrays":[2],"(FPGAs)":[3],"and":[4,46,56,62,66,101,115],"Single-Instruction":[5],"MultipleData":[6],"(SIMD)":[7],"processing":[8],"arrays":[9,103,119],"share":[10],"many":[11],"architectural":[12],"features.":[13],"In":[14,32],"both":[15,44],"architectures,":[16],"an":[17],"array":[18,40,60,84,107],"of":[19],"simple,":[20],"fine-grained":[21],"logic":[22],"elements":[23],"is":[24],"employed":[25],"to":[26,126],"provide":[27,127],"high-speed,":[28],"customizable,":[29],"bit-wise":[30],"computation.":[31],"this":[33,50],"paper,":[34],"we":[35,52],"present":[36],"a":[37,105],"unified":[38,76],"computational":[39],"model":[41,77],"which":[42,68,94],"encompasses":[43],"FPGAs":[45,100],"SIMD":[47,102,118],"arrays.":[48],"Within":[49],"framework,":[51],"examine":[53],"the":[54,73,88,96],"differences":[55],"similarities":[57],"between":[58,72],"these":[59],"structures":[61],"touch":[63],"upon":[64],"techniques":[65],"lessons":[67],"can":[69],"be":[70],"transfered":[71],"architectures.":[74,85],"The":[75],"also":[78],"exposes":[79],"promising":[80],"prospects":[81],"for":[82],"hybrid":[83],"We":[86],"introduce":[87],"Dynamically":[89],"Programmable":[90],"Array":[92],"(DPGA)":[93],"combines":[95],"best":[97],"features":[98],"from":[99],"into":[104],"single":[106],"architecture.":[108],"1":[109],"Introduction":[110],"FPGA-based":[111],"custom":[112],"computing":[113],"engines":[114],"massively":[116],"parallel":[117],"[Gea91,":[120],"Bol93,":[121],"BRV93]":[122],"have":[123],"been":[124],"demonstrated":[125],"supercomputer-class":[128],"performance":[129],"on":[130],"some":[131],"tasks":[132],"a...":[133]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2026-11-08T12:12:28.789561","created_date":"2016-06-24T00:00:00"}