{"id":"https://openalex.org/W384580792","doi":null,"title":"CBM: Core Based Memory Scheduling method","display_name":"CBM: Core Based Memory Scheduling method","publication_year":2012,"publication_date":"2012-07-25","ids":{"openalex":"https://openalex.org/W384580792","mag":"384580792"},"language":"en","primary_location":{"id":"mag:384580792","doi":null,"is_oa":false,"landing_page_url":"http://ci.nii.ac.jp/naid/110009425021","pdf_url":null,"source":{"id":"https://openalex.org/S4306417701","display_name":"Applied Reconfigurable Computing","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Applied Reconfigurable Computing","raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016708103","display_name":"Hosokawa Kohei","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hosokawa Kohei","raw_affiliation_strings":["The University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103071867","display_name":"Yasuo Ishii","orcid":"https://orcid.org/0000-0002-5952-0276","observed_orcids":["https://orcid.org/0000-0002-5952-0276"]},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasuo Ishii","raw_affiliation_strings":["The University of Tokyo, Tokyo, Japan"],"raw_orcid":"https://orcid.org/0000-0002-5952-0276","affiliations":[{"raw_affiliation_string":"The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110610652","display_name":"Inaba Mary","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Inaba Mary","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5112110720","display_name":"Kei Hiraki","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kei Hiraki","raw_affiliation_strings":["The University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2012","issue":"9","first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.0005000000237487257,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-access-scheduling","display_name":"memory scheduling","score":0.6669999957084656},{"id":"https://openalex.org/keywords/multi-core-processors","display_name":"multi-core processors","score":0.8830000162124634},{"id":"https://openalex.org/keywords/private-caches","display_name":"private caches","score":0.6859999895095825},{"id":"https://openalex.org/keywords/memory-controller","display_name":"memory controller","score":0.47099998593330383},{"id":"https://openalex.org/keywords/fairness","display_name":"fairness","score":0.3009999990463257},{"id":"https://openalex.org/keywords/throughput","display_name":"throughput","score":0.421999990940094}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8388122320175171},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.6662404537200928},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5679452419281006},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.5162503719329834},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.512087345123291},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.47194617986679077},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.4575049877166748},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4354248642921448},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4221237897872925},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41415542364120483},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.3167807161808014},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.26428863406181335},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2597016990184784},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.20326733589172363},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08335995674133301},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:384580792","doi":null,"is_oa":false,"landing_page_url":"http://ci.nii.ac.jp/naid/110009425021","pdf_url":null,"source":{"id":"https://openalex.org/S4306417701","display_name":"Applied Reconfigurable Computing","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Applied Reconfigurable Computing","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W1964316448"],"related_works":["https://openalex.org/W2055551669","https://openalex.org/W2941585681","https://openalex.org/W1488010588","https://openalex.org/W2050347968","https://openalex.org/W2963541813","https://openalex.org/W7098164106","https://openalex.org/W2159908132","https://openalex.org/W2130507983","https://openalex.org/W1979062512","https://openalex.org/W2012551760"],"abstract_inverted_index":{"In":[0],"modern":[1],"chip-multiprocessor":[2],"systems,":[3],"DRAM":[4,20,24],"is":[5,121],"shared":[6],"among":[7],"multiple":[8],"threads.":[9],"The":[10],"memory":[11,25,30,47,51,102,132,163,202,219],"scheduler":[12,144],"must":[13],"resolve":[14],"the":[15,19,29,37,44,73,83,91,94,125,135,142,150,156,161,166,175,187,196,201,206,226,236,244,266],"inter-thread":[16],"contention":[17],"for":[18,36,112,134],"effectiveness.":[21],"Previously":[22],"proposed":[23],"schedulers":[26],"have":[27],"calculated":[28],"access":[31],"intensity":[32],"of":[33,46,93,115,127,179,209,246],"each":[34,116,131,146,180,210],"thread":[35,84,197],"priority":[38,95,136,143,198,224,237],"scheduling.":[39],"Existing":[40],"methods[2],":[41],"[3]":[42],"analyze":[43],"number":[45],"requests":[48],"served":[49],"in":[50,216],"controller":[52,203],"to":[53,81,123,140,194,255],"get":[54],"memory-intensity,":[55],"but":[56,76,204],"these":[57],"methods":[58],"lack":[59],"prediction":[60,74],"accuracy.":[61],"TCM[1]":[62],"avoids":[63],"this":[64],"problem":[65],"by":[66,154,242],"using":[67,243],"MPKI":[68],"information.":[69],"TCM":[70,89],"can":[71,173,185,222],"improve":[72],"accuracy,":[75],"takes":[77],"very":[78],"long":[79],"cycles":[80],"update":[82],"priority.":[85],"As":[86],"a":[87,100],"result,":[88],"lacks":[90],"timeliness":[92,234],"prediction.":[96],"This":[97],"paper":[98],"presents":[99],"new":[101,162],"scheduling":[103,258],"method,":[104],"Core-Based":[105],"Memory":[106,247],"scheduling(CBM),":[107],"which":[108],"utilizes":[109],"core":[110,151,181],"information":[111,178],"memory-intensity":[113,188],"evaluation":[114],"thread.":[117],"Our":[118],"key":[119],"idea":[120],"1)":[122],"refer":[124],"distance":[126,159],"instruction":[128,157,176],"count":[129],"between":[130,160],"request":[133,164],"calculation,":[137],"and":[138,165,251,269],"2)":[139],"place":[141],"on":[145,200,205,235],"core.":[147,211],"CBM":[148,172,191,221,231,241,263],"judges":[149],"calculation":[152],"progress":[153,177],"comparing":[155],"counter":[158],"last":[167],"one.":[168],"By":[169,212],"doing":[170,213],"so,":[171,214],"utilize":[174],"directly,":[182],"thus":[183],"we":[184],"predict":[186],"more":[189],"accurately.":[190],"also":[192],"proposes":[193],"calculate":[195],"not":[199],"private":[207],"cache":[208],"even":[215],"concurrent":[217],"many-channel":[218],"system,":[220],"decide":[223],"without":[225],"heavy":[227],"inter-channel":[228],"communication.":[229],"Therefore,":[230],"accomplishes":[232],"high":[233],"update.":[238],"We":[239,260],"evaluate":[240],"workloads":[245],"Scheduling":[248],"Championship":[249],"(MSC)":[250],"compare":[252],"its":[253],"performance":[254],"two":[256],"existing":[257],"algorithms.":[259],"found":[261],"that":[262],"achieves":[264],"both":[265],"best":[267],"throughput":[268],"fairness.":[270]},"counts_by_year":[],"updated_date":"2026-09-26T08:19:03.415552","created_date":"2016-06-24T00:00:00"}
