{"id":"https://openalex.org/W36045043","doi":null,"title":"Fault Aware Instruction Placement for Static Architectures","display_name":"Fault Aware Instruction Placement for Static Architectures","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W36045043","mag":"36045043"},"language":"en","primary_location":{"id":"pmh:oai:CiteSeerX.psu:10.1.1.62.6911","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.62.6911","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.utexas.edu/users/lin/papers/hpcri05.pdf","raw_type":"text"},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084331444","display_name":"Premkishore Shivakumar","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Premkishore Shivakumar","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039645586","display_name":"Divya P. Gulati","orcid":"https://orcid.org/0009-0003-5181-4880","observed_orcids":["https://orcid.org/0009-0003-5181-4880"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Divya Gulati","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0009-0003-5181-4880","affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052763112","display_name":"Calvin Lin","orcid":"https://orcid.org/0000-0001-7716-2102","observed_orcids":["https://orcid.org/0000-0001-7716-2102"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Calvin Lin","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0001-7716-2102","affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5063354509","display_name":"Stephen W. Keckler","orcid":"https://orcid.org/0000-0001-6701-6099","observed_orcids":["https://orcid.org/0000-0001-6701-6099"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Stephen W. Keckler","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0001-6701-6099","affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.00857032,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.5195000171661377,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.5195000171661377,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.16380000114440918,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.08609999716281891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fault-reconfiguration","display_name":"fault reconfiguration","score":0.6380000114440918},{"id":"https://openalex.org/keywords/spatial-redundancy","display_name":"spatial redundancy","score":0.6959999799728394},{"id":"https://openalex.org/keywords/microprocessor-reliability","display_name":"microprocessor reliability","score":0.5640000104904175},{"id":"https://openalex.org/keywords/production-yield","display_name":"production yield","score":0.4300000071525574}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8195686340332031},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.596823513507843},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5880743265151978},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.5627095103263855},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4930057227611542},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.48914244771003723},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.47308260202407837},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.470253586769104},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4654088318347931},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.41417187452316284},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.41143739223480225},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36441588401794434},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15110057592391968},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12191146612167358},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:CiteSeerX.psu:10.1.1.62.6911","doi":null,"is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.62.6911","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.cs.utexas.edu/users/lin/papers/hpcri05.pdf","raw_type":"text"},{"id":"mag:36045043","doi":null,"is_oa":false,"landing_page_url":"https://www.cs.utexas.edu/~skeckler/pubs/HPCRI05.pdf","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W2014853465","https://openalex.org/W2083868341","https://openalex.org/W2094593152","https://openalex.org/W2102480715","https://openalex.org/W2116299797","https://openalex.org/W2125067970","https://openalex.org/W2147345262","https://openalex.org/W2151845324","https://openalex.org/W2153882047","https://openalex.org/W2157373341"],"related_works":["https://openalex.org/W7096861637","https://openalex.org/W2053207314","https://openalex.org/W2562245764","https://openalex.org/W1555167880","https://openalex.org/W2055511795","https://openalex.org/W2137680068","https://openalex.org/W4256410614","https://openalex.org/W1534468287","https://openalex.org/W2344180461","https://openalex.org/W2565965768"],"abstract_inverted_index":{"Aggressive":[0],"technology":[1],"scaling,":[2],"rising":[3],"clock":[4],"frequencies,":[5],"and":[6,19,47,133],"the":[7,57,66,83,107,128,140,150,155,160,176],"continued":[8],"increase":[9],"in":[10,27,61,116,125,139,159,187],"microprocessor":[11,30],"power":[12],"density":[13],"threaten":[14],"both":[15],"manufacturing":[16],"yield":[17],"rates":[18],"long-term":[20],"reliability":[21,50],"of":[22,90,94,100,166],"integrated":[23],"circuits.":[24],"While":[25],"defects":[26],"dynamically":[28,115],"scheduled":[29],"architectures":[31,43],"can":[32,69,131,148,174],"be":[33],"tolerated":[34],"using":[35],"mechanisms":[36],"that":[37,102,135,147,171],"are":[38,103,112],"transparent":[39],"to":[40,55,65,179],"software,":[41],"static":[42,63],"create":[44],"different":[45],"opportunities":[46],"challenges":[48],"for":[49],"management.":[51],"This":[52],"paper":[53],"proposes":[54],"expose":[56],"defective":[58],"hardware":[59],"configuration":[60],"a":[62,91,164],"architecture":[64,85],"compiler,":[67],"which":[68,111,126],"perform":[70],"efficient":[71],"fault":[72,122],"reconfiguration":[73],"through":[74],"intelligent":[75],"instruction":[76],"scheduling.":[77],"We":[78,119,143],"conducted":[79],"our":[80,172],"studies":[81],"on":[82,106],"TRIPS":[84],"whose":[86],"computation":[87,129,161],"core":[88],"consists":[89],"two-dimensional":[92],"array":[93],"ALUs.":[95],"The":[96],"compiler":[97],"generates":[98],"blocks":[99],"instructions":[101],"statically":[104],"placed":[105],"distributed":[108],"ALU":[109],"array,":[110],"then":[113],"executed":[114],"dataflow":[117],"order.":[118],"consider":[120],"two":[121],"models,":[123],"one":[124],"only":[127],"elements":[130],"fail,":[132],"another":[134],"also":[136],"allows":[137],"faults":[138,183],"communication":[141],"channels.":[142],"examine":[144],"scheduling":[145],"algorithms":[146,173],"avoid":[149],"faulty":[151],"resources":[152],"by":[153],"exploiting":[154],"spatial":[156],"redundancy":[157],"inherent":[158],"substrate.":[162],"For":[163],"set":[165],"microbenchmarks,":[167],"preliminary":[168],"results":[169],"demonstrate":[170],"reschedule":[175],"assembly":[177],"code":[178],"tolerate":[180],"execution":[181],"unit":[182],"with":[184],"negligible":[185],"loss":[186],"performance.":[188],"1":[189]},"counts_by_year":[],"updated_date":"2026-09-22T06:50:58.402377","created_date":"2016-06-24T00:00:00"}
