{"id":"https://openalex.org/W3209159293","doi":"https://doi.org/10.23919/eos/esd52038.2021.9574756","title":"NBL Causing Low Latch-up Immunity between HV-PMOS and LV-P/NMOS in a 0.15-\u00b5m BCD Process","display_name":"NBL Causing Low Latch-up Immunity between HV-PMOS and LV-P/NMOS in a 0.15-\u00b5m BCD Process","publication_year":2021,"publication_date":"2021-09-26","ids":{"openalex":"https://openalex.org/W3209159293","doi":"https://doi.org/10.23919/eos/esd52038.2021.9574756","mag":"3209159293"},"language":"en","primary_location":{"id":"doi:10.23919/eos/esd52038.2021.9574756","doi":"https://doi.org/10.23919/eos/esd52038.2021.9574756","is_oa":false,"landing_page_url":"https://doi.org/10.23919/eos/esd52038.2021.9574756","pdf_url":null,"source":{"id":"https://openalex.org/S7407088814","display_name":"Annual EOS/ESD Symposium (EOS/ESD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 43rd Annual EOS/ESD Symposium (EOS/ESD)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112675166","display_name":"Chaoyang Chen","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]},{"id":"https://openalex.org/I4210151006","display_name":"Vanguard International Semiconductor (Taiwan)","ror":"https://ror.org/04jmkm342","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210151006"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chao-Yang Chen","raw_affiliation_strings":["Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","Vanguard International Semiconductor Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]},{"raw_affiliation_string":"Vanguard International Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210151006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040031014","display_name":"Jian\u2010Hsing Lee","orcid":"https://orcid.org/0000-0001-5903-6890","observed_orcids":["https://orcid.org/0000-0001-5903-6890"]},"institutions":[{"id":"https://openalex.org/I4210151006","display_name":"Vanguard International Semiconductor (Taiwan)","ror":"https://ror.org/04jmkm342","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210151006"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jian-Hsing Lee","raw_affiliation_strings":["Vanguard International Semiconductor Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Vanguard International Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210151006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009081229","display_name":"Karuna Nidhi","orcid":"https://orcid.org/0000-0003-4512-9580","observed_orcids":["https://orcid.org/0000-0003-4512-9580"]},"institutions":[{"id":"https://openalex.org/I4210151006","display_name":"Vanguard International Semiconductor (Taiwan)","ror":"https://ror.org/04jmkm342","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210151006"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Karuna Nidhi","raw_affiliation_strings":["Vanguard International Semiconductor Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Vanguard International Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210151006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012097238","display_name":"Tzer-Yaa Bin","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210151006","display_name":"Vanguard International Semiconductor (Taiwan)","ror":"https://ror.org/04jmkm342","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210151006"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tzer-Yaa Bin","raw_affiliation_strings":["Vanguard International Semiconductor Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Vanguard International Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210151006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015049808","display_name":"Geeng-Lih Lin","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210151006","display_name":"Vanguard International Semiconductor (Taiwan)","ror":"https://ror.org/04jmkm342","country_code":"TW","type":"company","lineage":["https://openalex.org/I4210151006"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Geeng-Lih Lin","raw_affiliation_strings":["Vanguard International Semiconductor Corporation, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Vanguard International Semiconductor Corporation, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I4210151006"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043540734","display_name":"Ming\u2010Dou Ker","orcid":"https://orcid.org/0000-0003-3622-181X","observed_orcids":["https://orcid.org/0000-0003-3622-181X"]},"institutions":[{"id":"https://openalex.org/I148366613","display_name":"National Yang Ming Chiao Tung University","ror":"https://ror.org/00se2k293","country_code":"TW","type":"education","lineage":["https://openalex.org/I148366613"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Dou Ker","raw_affiliation_strings":["Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I148366613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.7737,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63851578,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.0015999999595806003,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10361","display_name":"Silicon Carbide Semiconductor Technologies","score":0.0008999999845400453,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/latch-up-immunity","display_name":"latch-up immunity","score":0.9319999814033508},{"id":"https://openalex.org/keywords/bcd-process","display_name":"BCD process","score":0.8410000205039978}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.9525531530380249},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.9471557140350342},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5593459606170654},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5108470320701599},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4568917751312256},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4398866891860962},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4374414086341858},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.43440788984298706},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3657831847667694},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.32025301456451416},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24766460061073303}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/eos/esd52038.2021.9574756","doi":"https://doi.org/10.23919/eos/esd52038.2021.9574756","is_oa":false,"landing_page_url":"https://doi.org/10.23919/eos/esd52038.2021.9574756","pdf_url":null,"source":{"id":"https://openalex.org/S7407088814","display_name":"Annual EOS/ESD Symposium (EOS/ESD)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 43rd Annual EOS/ESD Symposium (EOS/ESD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1494199278","https://openalex.org/W2005793633","https://openalex.org/W2096720663","https://openalex.org/W2135846180","https://openalex.org/W2143655922","https://openalex.org/W2345223022","https://openalex.org/W2726471679","https://openalex.org/W2899282284","https://openalex.org/W2915099510","https://openalex.org/W2945628190","https://openalex.org/W2946653072","https://openalex.org/W4251109733"],"related_works":["https://openalex.org/W4399486782","https://openalex.org/W2899282284","https://openalex.org/W2046336145","https://openalex.org/W3159629332","https://openalex.org/W4390816691","https://openalex.org/W4289950764","https://openalex.org/W2726471679","https://openalex.org/W4308092256","https://openalex.org/W3168458347","https://openalex.org/W2889320750"],"abstract_inverted_index":{"The":[0,20,82],"N-buried":[1],"layer":[2,22],"(NBL)":[3],"causing":[4],"low":[5],"latch-up":[6,75,80,83],"immunity":[7],"between":[8,67,87],"the":[9,29,32,46,50,59,63,78,88],"HV-PMOS":[10],"and":[11,53],"LV-PMOS":[12],"/":[13],"LV-NMOS":[14],"is":[15],"studied":[16],"in":[17],"this":[18],"work.":[19],"NBL":[21,97],"has":[23],"been":[24],"often":[25],"used":[26],"to":[27,41],"isolate":[28],"circuits":[30,52,55,90],"from":[31],"common":[33,47],"p-substrate":[34],"for":[35],"operating":[36],"at":[37],"different":[38,92],"voltages,":[39],"or":[40,84],"avoid":[42],"noise":[43],"coupling":[44],"through":[45],"p-substrate.":[48],"As":[49],"HV":[51],"LV":[54],"integrated":[56],"together":[57],"on":[58],"same":[60],"silicon":[61],"chip,":[62],"parasitic":[64],"latchup":[65],"paths":[66],"them":[68],"would":[69],"be":[70,99],"easily":[71],"triggered":[72],"into":[73],"a":[74],"state":[76],"under":[77],"current-trigger":[79],"test.":[81],"latch-up-like":[85],"issues":[86],"neighbor":[89],"with":[91],"power":[93],"domains":[94],"surrounding":[95],"by":[96],"must":[98],"paid":[100],"attention.":[101]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-10-30T12:39:25.321706","created_date":"2021-11-08T00:00:00"}
