{"id":"https://openalex.org/W3180949432","doi":"https://doi.org/10.1109/aspdac.1995.486381","title":"The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor","display_name":"The DUAL-EVAL hardware description language and its use in the formal specification and verification of the FM9001 microprocessor","publication_year":2002,"publication_date":"2002-11-19","ids":{"openalex":"https://openalex.org/W3180949432","doi":"https://doi.org/10.1109/aspdac.1995.486381","mag":"3180949432"},"language":"en","primary_location":{"id":"doi:10.1109/aspdac.1995.486381","doi":"https://doi.org/10.1109/aspdac.1995.486381","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.1995.486381","pdf_url":null,"source":{"id":"https://openalex.org/S4363608791","display_name":"Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084447019","display_name":"Warren A. Hunt","orcid":"https://orcid.org/0009-0004-1444-2544","observed_orcids":["https://orcid.org/0009-0004-1444-2544"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"W.A. Hunt","raw_affiliation_strings":["Computational Logic, Inc., Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computational Logic, Inc., Austin, TX, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031518845","display_name":"Bishop C. Brock","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"B.C. Brock","raw_affiliation_strings":["Computational Logic, Inc., Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computational Logic, Inc., Austin, TX, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.30801586,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":"408","issue":null,"first_page":"637","last_page":"642"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.7045999765396118,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.7045999765396118,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.1858000010251999,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10126","display_name":"Logic, programming, and type systems","score":0.04919999837875366,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hardware-description-languages","display_name":"hardware description languages","score":0.8519999980926514},{"id":"https://openalex.org/keywords/formal-specification","display_name":"formal specification","score":0.7590000033378601},{"id":"https://openalex.org/keywords/formal-verification","display_name":"formal verification","score":0.9649999737739563},{"id":"https://openalex.org/keywords/mealy-machines","display_name":"Mealy machines","score":0.8539999723434448},{"id":"https://openalex.org/keywords/synchronous-circuits","display_name":"synchronous circuits","score":0.4959999918937683},{"id":"https://openalex.org/keywords/hierarchical-simulation","display_name":"hierarchical simulation","score":0.7730000019073486},{"id":"https://openalex.org/keywords/behavioral-specification","display_name":"behavioral specification","score":0.8029999732971191},{"id":"https://openalex.org/keywords/mechanical-proof","display_name":"mechanical proof","score":0.6610000133514404},{"id":"https://openalex.org/keywords/cmos-asic","display_name":"CMOS ASIC","score":0.9739999771118164}],"concepts":[{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.7945042252540588},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7635851502418518},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7197525501251221},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.6243080496788025},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5195775032043457},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.48291251063346863},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.47485116124153137},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4313036799430847},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4213643968105316},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39249691367149353},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14233455061912537},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/aspdac.1995.486381","doi":"https://doi.org/10.1109/aspdac.1995.486381","is_oa":false,"landing_page_url":"https://doi.org/10.1109/aspdac.1995.486381","pdf_url":null,"source":{"id":"https://openalex.org/S4363608791","display_name":"Asia and South Pacific Design Automation Conference (ASP-DAC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":29,"referenced_works":["https://openalex.org/W2768743","https://openalex.org/W74334858","https://openalex.org/W85132038","https://openalex.org/W1480077489","https://openalex.org/W1496551897","https://openalex.org/W1503170978","https://openalex.org/W1518675260","https://openalex.org/W1521083034","https://openalex.org/W1527057751","https://openalex.org/W1533883930","https://openalex.org/W1535456172","https://openalex.org/W1549345379","https://openalex.org/W1769977300","https://openalex.org/W1830531781","https://openalex.org/W1986558678","https://openalex.org/W2035030296","https://openalex.org/W2047932652","https://openalex.org/W2084715426","https://openalex.org/W2095572512","https://openalex.org/W2099078002","https://openalex.org/W2101241724","https://openalex.org/W2103709633","https://openalex.org/W2107517480","https://openalex.org/W2169991924","https://openalex.org/W2485170588","https://openalex.org/W2612719351","https://openalex.org/W4300021588","https://openalex.org/W4302604543","https://openalex.org/W6603043795"],"related_works":["https://openalex.org/W2169991924","https://openalex.org/W7099990318","https://openalex.org/W4234103458","https://openalex.org/W1769977300","https://openalex.org/W4253305122","https://openalex.org/W6991576079","https://openalex.org/W3004937574","https://openalex.org/W1970825584","https://openalex.org/W1984634196","https://openalex.org/W2132055325"],"abstract_inverted_index":{"We":[0,20],"present":[1],"an":[2],"introduction":[3],"to":[4,42],"the":[5,23,33],"DUAL-EVAL":[6,10,34],"hardware":[7],"description":[8],"language.":[9],"is":[11],"a":[12,43,52],"hierarchical,":[13],"occurrence-oriented":[14],"simulator":[15],"for":[16],"synchronous":[17],"Mealy":[18],"machines.":[19],"briefly":[21],"describe":[22],"FM9001":[24,47],"microprocessor,":[25],"whose":[26],"design":[27],"has":[28,48],"been":[29,49],"formally":[30],"specified":[31],"with":[32,40],"language":[35],"and":[36,55],"mechanically":[37],"proved":[38],"correct":[39],"respect":[41],"behavioral":[44],"specification.":[45],"The":[46],"fabricated":[50],"as":[51],"CMOS":[53],"ASIC":[54],"tested":[56],"extensively.":[57]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2021-07-19T00:00:00"}
