{"id":"https://openalex.org/W3166128015","doi":null,"title":"Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits","display_name":"Performance Analysis of Clock Gating Designs in Low Power Vlsi Circuits","publication_year":2021,"publication_date":"2021-05-31","ids":{"openalex":"https://openalex.org/W3166128015","mag":"3166128015"},"language":"en","primary_location":{"id":"mag:3166128015","doi":null,"is_oa":false,"landing_page_url":"http://thedesignengineering.com/index.php/DE/article/view/1810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Design Engineering","raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014234800","display_name":"Ch Haritha","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ch Haritha","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5055113310","display_name":"M. Devanathan","orcid":"https://orcid.org/0000-0001-7536-0463","observed_orcids":["https://orcid.org/0000-0001-7536-0463"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Devanathan","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.00039999998989515007,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-gating","display_name":"clock gating","score":1.0},{"id":"https://openalex.org/keywords/low-power-vlsi-design","display_name":"low-power VLSI design","score":0.8399999737739563},{"id":"https://openalex.org/keywords/clock-distribution","display_name":"clock distribution","score":0.8069999814033508},{"id":"https://openalex.org/keywords/dynamic-power","display_name":"dynamic power","score":0.7609999775886536},{"id":"https://openalex.org/keywords/leakage-power","display_name":"leakage power","score":0.9950000047683716},{"id":"https://openalex.org/keywords/clock-power-reduction","display_name":"clock power reduction","score":0.4659999907016754},{"id":"https://openalex.org/keywords/flip-flops","display_name":"flip-flops","score":0.7020000219345093}],"concepts":[{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.965359628200531},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7932991981506348},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6922268271446228},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.6906322240829468},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.6322264671325684},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.6054601073265076},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.5636533498764038},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5630783438682556},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4816955029964447},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4780902564525604},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.4294726252555847},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.386738121509552},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.38313111662864685},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.30442261695861816}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:3166128015","doi":null,"is_oa":false,"landing_page_url":"http://thedesignengineering.com/index.php/DE/article/view/1810","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"Design Engineering","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5378999710083008,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2609613993","https://openalex.org/W4285171868","https://openalex.org/W4386948726","https://openalex.org/W7139101047","https://openalex.org/W7128805249","https://openalex.org/W2534441289","https://openalex.org/W4205570926","https://openalex.org/W6922644465","https://openalex.org/W4244525914","https://openalex.org/W59924950"],"abstract_inverted_index":{"Power":[0],"utilization":[1],"is":[2,11,34,41,69,136],"a":[3,58,70],"significant":[4],"bottleneck":[5],"of":[6,15,30,43,124,133],"system":[7,39,62],"performance":[8],"and":[9,25,48,130],"it":[10],"recorded":[12],"as":[13],"one":[14],"the":[16,31,37,44,80,84,93,98,108,115],"main":[17],"three":[18],"difficulties":[19],"in":[20],"International":[21],"Technology":[22],"Roadmap.":[23],"By":[24],"by,":[26],"an":[27],"enormous":[28],"part":[29],"on-chip":[32],"power":[33,60,95,117,127,135],"devoured":[35],"by":[36,78,96,118],"clock":[38,45,67,81,94,99,111,125],"which":[40,113],"made":[42],"distribution":[46],"network":[47],"flip":[49],"flops.":[50],"In":[51],"this":[52],"paper,":[53],"different":[54],"plan":[55],"procedures":[56],"for":[57],"low":[59],"clocking":[61],"are":[63],"overviewed.":[64],"Among":[65],"them":[66],"gating":[68,90,112],"successful":[71],"method":[72],"to":[73],"lessen":[74],"dynamic":[75],"force":[76],"scattering,":[77],"eliminating":[79],"signal":[82],"when":[83],"circuit":[85],"isn't":[86],"being":[87],"used.":[88],"Clock":[89],"will":[91],"reduce":[92],"trimming":[97],"tree":[100],"along":[101],"with":[102],"including":[103],"some":[104],"new":[105],"logic":[106],"into":[107],"circuit.We":[109],"noticed":[110],"diminishes":[114],"overall":[116],"around":[119],"75%.":[120],"A":[121],"75.12%":[122],"decrease":[123,132],"driving":[126],"(Dynamic":[128],"power)":[129],"6.4%":[131],"leakage":[134],"accomplished.":[137]},"counts_by_year":[],"updated_date":"2026-09-21T07:43:02.447757","created_date":"2021-06-22T00:00:00"}
