{"id":"https://openalex.org/W3141213637","doi":"https://doi.org/10.1109/isca.2006.10","title":"Area-Performance Trade-offs in Tiled Dataflow Architectures","display_name":"Area-Performance Trade-offs in Tiled Dataflow Architectures","publication_year":2006,"publication_date":"2006-01-01","ids":{"openalex":"https://openalex.org/W3141213637","doi":"https://doi.org/10.1109/isca.2006.10","mag":"3141213637"},"language":"en","primary_location":{"id":"doi:10.1109/isca.2006.10","doi":"https://doi.org/10.1109/isca.2006.10","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2006.10","pdf_url":null,"source":{"id":"https://openalex.org/S4393916863","display_name":"Proceedings - International Symposium on Computer Architecture/Proceedings","issn_l":"1063-6897","issn":["1063-6897"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["norway-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"33rd International Symposium on Computer Architecture (ISCA'06)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005764203","display_name":"Steven Swanson","orcid":"https://orcid.org/0000-0002-5896-1037","observed_orcids":["https://orcid.org/0000-0002-5896-1037"]},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Swanson","raw_affiliation_strings":["Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024883549","display_name":"Andrew R. Putnam","orcid":"https://orcid.org/0000-0001-5241-5695","observed_orcids":["https://orcid.org/0000-0001-5241-5695"]},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Putnam","raw_affiliation_strings":["Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066291981","display_name":"Michele Mercaldi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Mercaldi","raw_affiliation_strings":["Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057277134","display_name":"Ken Michelson","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Michelson","raw_affiliation_strings":["Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":null,"display_name":"A. Petersen","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Petersen","raw_affiliation_strings":["Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019748631","display_name":"Andrew Schwerin","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Schwerin","raw_affiliation_strings":["Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063231555","display_name":"Mark Oskin","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Oskin","raw_affiliation_strings":["Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051475447","display_name":"Susan J. Eggers","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.J. Eggers","raw_affiliation_strings":["Computer Science & Engineering, University of Washington, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer Science & Engineering, University of Washington, USA","institution_ids":["https://openalex.org/I201448701"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I201448701"],"apc_list":null,"apc_paid":null,"fwci":2.7571,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.91252547,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"314","last_page":"326"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7416999936103821,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.7416999936103821,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.1826000064611435,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.03500000014901161,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/area-performance-trade-off","display_name":"area-performance trade-off","score":0.8790000081062317},{"id":"https://openalex.org/keywords/multi-threaded-workloads","display_name":"multi-threaded workloads","score":0.6890000104904175},{"id":"https://openalex.org/keywords/processor-scalability","display_name":"processor scalability","score":0.5960000157356262},{"id":"https://openalex.org/keywords/cycle-level-simulation","display_name":"cycle-level simulation","score":0.5609999895095825},{"id":"https://openalex.org/keywords/rtl-synthesis","display_name":"RTL synthesis","score":0.38199999928474426}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6821939945220947},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6697239279747009},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.5784986019134521},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5035197138786316},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35726988315582275},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.16001924872398376}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/isca.2006.10","doi":"https://doi.org/10.1109/isca.2006.10","is_oa":false,"landing_page_url":"https://doi.org/10.1109/isca.2006.10","pdf_url":null,"source":{"id":"https://openalex.org/S4393916863","display_name":"Proceedings - International Symposium on Computer Architecture/Proceedings","issn_l":"1063-6897","issn":["1063-6897"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["norway-1"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"33rd International Symposium on Computer Architecture (ISCA'06)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1505816907","https://openalex.org/W1571640363","https://openalex.org/W1579339160","https://openalex.org/W1620770595","https://openalex.org/W1979352334","https://openalex.org/W1984527041","https://openalex.org/W1985297731","https://openalex.org/W2018885404","https://openalex.org/W2045036428","https://openalex.org/W2051676750","https://openalex.org/W2112590555","https://openalex.org/W2150007533","https://openalex.org/W2154323564","https://openalex.org/W2157373341","https://openalex.org/W2169589589","https://openalex.org/W2171532807","https://openalex.org/W3139889547","https://openalex.org/W4236272793","https://openalex.org/W4239997146","https://openalex.org/W4242368470","https://openalex.org/W4242861182","https://openalex.org/W4245348408","https://openalex.org/W4249006057","https://openalex.org/W4249868603"],"related_works":["https://openalex.org/W7099454755","https://openalex.org/W7099904097","https://openalex.org/W2142501475","https://openalex.org/W2165840702","https://openalex.org/W7096654145","https://openalex.org/W7097387271","https://openalex.org/W7100856399","https://openalex.org/W2801167919","https://openalex.org/W2222307716","https://openalex.org/W2097378962"],"abstract_inverted_index":{"Tiled":[0],"architectures,":[1],"such":[2,53],"as":[3],"RAW,":[4],"SmartMemories,":[5],"TRIPS,":[6],"and":[7,20,63,109,132],"WaveScalar,":[8],"promise":[9],"to":[10,66,103,112],"address":[11],"several":[12],"issues":[13],"facing":[14],"conventional":[15],"processors,":[16],"including":[17],"complexity,":[18],"wire-delay,":[19],"performance.":[21,117],"The":[22],"basic":[23,39],"premise":[24],"of":[25,72],"these":[26],"architectures":[27],"is":[28],"that":[29,121,133],"larger,":[30],"higher-performance":[31],"implementations":[32],"can":[33],"be":[34],"constructed":[35],"by":[36],"replicating":[37],"the":[38,42,47,136],"tile":[40],"across":[41],"chip.":[43],"This":[44],"paper":[45],"explores":[46],"area-performance":[48],"trade-offs":[49],"when":[50],"designing":[51],"one":[52],"tiled":[54],"architecture,":[55],"WaveScalar.":[56],"We":[57,90],"use":[58],"a":[59,85],"synthesizable":[60],"RTL":[61],"model":[62],"cycle-level":[64],"simulator":[65],"perform":[67],"an":[68,126,147],"area/performance":[69],"pareto":[70],"analysis":[71,119],"over":[73],"200":[74],"WaveScalar":[75,96,134],"processor":[76,155],"designs":[77],"ranging":[78],"in":[79,129,141],"size":[80],"from":[81,101,110],"19mm2to":[82],"575mm2and":[83],"having":[84],"22":[86],"FO4":[87],"cycle":[88],"time.":[89],"demonstrate":[91],"that,":[92],"for":[93,106,115],"multi-threaded":[94],"workloads,":[95],"performance":[97,140],"scales":[98],"almost":[99],"ideally":[100],"19":[102],"101mm2when":[104],"optimized":[105,114],"area":[107,144],"efficiency":[108],"44":[111],"202mm2when":[113],"peak":[116],"Our":[118],"reveals":[120],"WaveScalar's":[122],"hierarchical":[123],"interconnect":[124],"plays":[125],"important":[127],"role":[128],"overall":[130],"scalability,":[131],"achieves":[135],"same":[137],"(or":[138],"higher)":[139],"substantially":[142],"less":[143],"than":[145],"either":[146],"aggressive":[148],"out-of-order":[149],"superscalar":[150],"or":[151],"Sun's":[152],"Niagara":[153],"CMP":[154]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":4},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":2}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2021-04-13T00:00:00"}
