{"id":"https://openalex.org/W3139748210","doi":"https://doi.org/10.1109/dac.1992.227848","title":"An engineering environment for hardware/software co-simulation","display_name":"An engineering environment for hardware/software co-simulation","publication_year":2003,"publication_date":"2003-01-02","ids":{"openalex":"https://openalex.org/W3139748210","doi":"https://doi.org/10.1109/dac.1992.227848","mag":"3139748210"},"language":"en","primary_location":{"id":"doi:10.1109/dac.1992.227848","doi":"https://doi.org/10.1109/dac.1992.227848","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac.1992.227848","pdf_url":null,"source":{"id":"https://openalex.org/S4210231368","display_name":"ACM/IEEE Design Automation Conference (DAC)","issn_l":"0738-100X","issn":["0738-100X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031010981","display_name":"D. Becker","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I114027177","display_name":"University of North Carolina at Chapel Hill","ror":"https://ror.org/0130frc33","country_code":"US","type":"education","lineage":["https://openalex.org/I114027177"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Becker","raw_affiliation_strings":["Department of Computer Science, University of North Carolina, Chapel Hill, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of North Carolina, Chapel Hill, USA","institution_ids":["https://openalex.org/I114027177"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101538383","display_name":"Raj K. Singh","orcid":"https://orcid.org/0009-0001-3986-2535","observed_orcids":["https://orcid.org/0009-0001-3986-2535"]},"institutions":[{"id":"https://openalex.org/I114027177","display_name":"University of North Carolina at Chapel Hill","ror":"https://ror.org/0130frc33","country_code":"US","type":"education","lineage":["https://openalex.org/I114027177"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R.K. Singh","raw_affiliation_strings":["Department of Computer Science, University of North Carolina, Chapel Hill, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of North Carolina, Chapel Hill, USA","institution_ids":["https://openalex.org/I114027177"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102966476","display_name":"Stephen G. Tell","orcid":"https://orcid.org/0000-0002-2166-1452","observed_orcids":["https://orcid.org/0000-0002-2166-1452"]},"institutions":[{"id":"https://openalex.org/I114027177","display_name":"University of North Carolina at Chapel Hill","ror":"https://ror.org/0130frc33","country_code":"US","type":"education","lineage":["https://openalex.org/I114027177"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S.G. Tell","raw_affiliation_strings":["Department of Computer Science, University of North Carolina, Chapel Hill, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of North Carolina, Chapel Hill, USA","institution_ids":["https://openalex.org/I114027177"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I114027177"],"apc_list":null,"apc_paid":null,"fwci":0.7016,"has_fulltext":false,"cited_by_count":65,"citation_normalized_percentile":{"value":0.70121131,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"129","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.0008999999845400453,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.000699999975040555,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hardware-software-co-simulation","display_name":"hardware/software co-simulation","score":0.9929999709129333},{"id":"https://openalex.org/keywords/software-debugging","display_name":"software debugging","score":0.5580000281333923},{"id":"https://openalex.org/keywords/hardware-simulation","display_name":"hardware simulation","score":0.8679999709129333},{"id":"https://openalex.org/keywords/high-performance-systems","display_name":"high-performance systems","score":0.7889999747276306},{"id":"https://openalex.org/keywords/system-design","display_name":"system design","score":0.7269999980926514}],"concepts":[{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7810965776443481},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.630731999874115},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.6213899254798889},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5628193020820618},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4784272313117981},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4459380805492401},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35753118991851807},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3122565448284149},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.09994247555732727}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/dac.1992.227848","doi":"https://doi.org/10.1109/dac.1992.227848","is_oa":false,"landing_page_url":"https://doi.org/10.1109/dac.1992.227848","pdf_url":null,"source":{"id":"https://openalex.org/S4210231368","display_name":"ACM/IEEE Design Automation Conference (DAC)","issn_l":"0738-100X","issn":["0738-100X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319798","host_organization_name":"Association for Computing Machinery","host_organization_lineage":["https://openalex.org/P4310319798"],"host_organization_lineage_names":["Association for Computing Machinery"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"[1992] Proceedings 29th ACM/IEEE Design Automation Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2004453135","https://openalex.org/W2073584931"],"related_works":["https://openalex.org/W2169369560","https://openalex.org/W3136508752","https://openalex.org/W2390741172","https://openalex.org/W4238593383","https://openalex.org/W2163033792","https://openalex.org/W7100299353","https://openalex.org/W7097842071","https://openalex.org/W2062454463","https://openalex.org/W2154932558","https://openalex.org/W2012438952"],"abstract_inverted_index":{"The":[0,35,50],"authors":[1],"describe":[2],"an":[3],"environment":[4,51],"supporting":[5],"concurrent":[6],"hardware":[7,32,48],"and":[8,30,45],"software":[9,29,43],"engineering":[10],"for":[11],"high":[12],"performance":[13],"systems.":[14],"In":[15],"place":[16],"of":[17],"a":[18,55],"conventional":[19],"bread-boarded":[20],"prototype,":[21],"they":[22],"used":[23],"distributed":[24],"communicating":[25],"processes":[26],"to":[27,33,41],"allow":[28],"simulated":[31],"interact.":[34],"Cadence":[36],"Verilog-XL":[37],"simulator":[38],"was":[39,52],"extended":[40],"enable":[42],"debugging":[44],"testing":[46],"using":[47],"simulation.":[49],"proven":[53],"during":[54],"successful":[56],"system":[57],"design.>":[58]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":2}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2021-04-13T00:00:00"}