{"id":"https://openalex.org/W3133674811","doi":"https://doi.org/10.1109/icjece.2020.3025198","title":"Fast Mapping and Updating Algorithms for a Binary CAM on FPGA","display_name":"Fast Mapping and Updating Algorithms for a Binary CAM on FPGA","publication_year":2021,"publication_date":"2021-01-01","ids":{"openalex":"https://openalex.org/W3133674811","doi":"https://doi.org/10.1109/icjece.2020.3025198","mag":"3133674811"},"language":"en","primary_location":{"id":"doi:10.1109/icjece.2020.3025198","doi":"https://doi.org/10.1109/icjece.2020.3025198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icjece.2020.3025198","pdf_url":null,"source":{"id":"https://openalex.org/S4210179864","display_name":"Canadian Journal of Electrical and Computer Engineering","issn_l":"0840-8688","issn":["0840-8688","2694-1783"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-c","norway-1","poland-20","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Canadian Journal of Electrical and Computer Engineering","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080611900","display_name":"Azhar Qazi","orcid":"https://orcid.org/0000-0002-1479-4177","observed_orcids":["https://orcid.org/0000-0002-1479-4177"]},"institutions":[{"id":"https://openalex.org/I4210112203","display_name":"CECOS University","ror":"https://ror.org/01xyxtp53","country_code":"PK","type":"education","lineage":["https://openalex.org/I4210112203"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Azhar Qazi","raw_affiliation_strings":["CECOS University of IT and Emerging Sciences, Peshawar, Pakistan"],"raw_orcid":"https://orcid.org/0000-0002-1479-4177","affiliations":[{"raw_affiliation_string":"CECOS University of IT and Emerging Sciences, Peshawar, Pakistan","institution_ids":["https://openalex.org/I4210112203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067307648","display_name":"Zahid Ullah","orcid":"https://orcid.org/0000-0002-5633-6764","observed_orcids":["https://orcid.org/0000-0002-5633-6764"]},"institutions":[{"id":"https://openalex.org/I4391767994","display_name":"Pak-Austria Fachhochschule: Institute of Applied Sciences and Technology","ror":"https://ror.org/05pgqgb54","country_code":"PK","type":"education","lineage":["https://openalex.org/I4391767994"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"Zahid Ullah","raw_affiliation_strings":["Pak-Austria Fachochschule: Institute of Applied Sciences and Technology, Haripur, Pakistan"],"raw_orcid":"https://orcid.org/0000-0002-5633-6764","affiliations":[{"raw_affiliation_string":"Pak-Austria Fachochschule: Institute of Applied Sciences and Technology, Haripur, Pakistan","institution_ids":["https://openalex.org/I4391767994"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005561476","display_name":"Abdul Basit Hafeez","orcid":"https://orcid.org/0000-0002-4458-8606","observed_orcids":["https://orcid.org/0000-0002-4458-8606"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Abdul Hafeez","raw_affiliation_strings":["University of Engineering and Technology, Jalozai Campus, Pakistan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Engineering and Technology, Jalozai Campus, Pakistan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2045,"currency":"USD","value_usd":2045},"apc_paid":null,"fwci":0.7824,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.71482746,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":"44","issue":"2","first_page":"156","last_page":"164"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/content-addressable-memory","display_name":"content-addressable memory","score":0.9890000224113464},{"id":"https://openalex.org/keywords/lookup-tables","display_name":"look-up table","score":0.902999997138977},{"id":"https://openalex.org/keywords/block-ram","display_name":"block RAM","score":0.7749999761581421},{"id":"https://openalex.org/keywords/xilinx-virtex-6","display_name":"Xilinx Virtex-6","score":0.8299999833106995},{"id":"https://openalex.org/keywords/ip-filtering","display_name":"IP filtering","score":0.656000018119812}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8261563777923584},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8118693828582764},{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7401653528213501},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6175829172134399},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5645381212234497},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5093284845352173},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5084701776504517},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5004959106445312},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4934803247451782},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.4906395971775055},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4184395372867584},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3913886845111847},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33156198263168335},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.2273096740245819},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08022713661193848},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/icjece.2020.3025198","doi":"https://doi.org/10.1109/icjece.2020.3025198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/icjece.2020.3025198","pdf_url":null,"source":{"id":"https://openalex.org/S4210179864","display_name":"Canadian Journal of Electrical and Computer Engineering","issn_l":"0840-8688","issn":["0840-8688","2694-1783"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-c","norway-1","poland-20","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Canadian Journal of Electrical and Computer Engineering","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1971423915","https://openalex.org/W1996635038","https://openalex.org/W1998915717","https://openalex.org/W2006115588","https://openalex.org/W2013406643","https://openalex.org/W2021260287","https://openalex.org/W2068933159","https://openalex.org/W2073209050","https://openalex.org/W2103664004","https://openalex.org/W2106867391","https://openalex.org/W2231737954","https://openalex.org/W2561621772","https://openalex.org/W2618376964","https://openalex.org/W2751813293","https://openalex.org/W2767585707","https://openalex.org/W2793595879","https://openalex.org/W2795975079","https://openalex.org/W2890805660","https://openalex.org/W2906604693","https://openalex.org/W2914935471","https://openalex.org/W2929407385","https://openalex.org/W2932879690","https://openalex.org/W2933246250","https://openalex.org/W2947178375","https://openalex.org/W3007580178","https://openalex.org/W4239721110"],"related_works":["https://openalex.org/W4386221490","https://openalex.org/W7171227970","https://openalex.org/W3033697055","https://openalex.org/W3176701885","https://openalex.org/W3205734318","https://openalex.org/W2587748659","https://openalex.org/W2947178375","https://openalex.org/W2380162260","https://openalex.org/W2795675301","https://openalex.org/W3028525919"],"abstract_inverted_index":{"Content-addressable":[0],"memories":[1,115],"(CAMs)":[2],"are":[3,30,102,179],"used":[4,32],"in":[5,67,71,77,86,134,145,148,152,160],"a":[6,98],"variety":[7],"of":[8,42,129],"applications,":[9],"such":[10,55],"as":[11,140],"IP":[12],"filtering,":[13],"data":[14],"compression,":[15],"and":[16,62,94,111,124,185],"artificial":[17],"neural":[18],"networks":[19],"due":[20],"to":[21,33,51,82,120,172,195],"its":[22],"high-speed":[23],"lookup.":[24],"Fast":[25],"field-programmable":[26],"gate":[27],"arrays":[28],"(FPGAs)":[29],"nowadays":[31],"emulate":[34,52,121],"CAMs.":[35,53,126],"These":[36],"CAM":[37,56,84,100,138,158,163],"emulations":[38],"either":[39],"make":[40],"use":[41,46],"logical":[43],"resources":[44],"or":[45],"memory":[47,149],"blocks":[48],"on":[49,117,181],"FPGAs":[50],"However,":[54],"emulation":[57],"suffers":[58],"from":[59],"slower":[60,75],"mapping":[61,93,123],"updating":[63,95,125,146,168],"mechanisms,":[64],"which":[65,104,143,170],"results":[66,187],"an":[68,141],"unacceptable":[69],"response":[70,76],"real-time":[72],"applications.":[73],"The":[74,127,176],"update":[78,174],"mechanism":[79],"is":[80],"proportionate":[81],"the":[83,87,130,137,153,156,162,167,186,190],"depth":[85,159],"schemes.":[88],"In":[89],"this":[90],"article,":[91],"fast":[92],"algorithms":[96,178],"for":[97],"binary":[99],"(FMU-BiCAM)":[101],"presented,":[103],"efficiently":[105],"utilizes":[106],"lookup":[107],"tables,":[108],"slice":[109],"registers,":[110],"block":[112],"random":[113],"access":[114],"(RAMs)":[116],"Xilinx":[118,182],"FPGA":[119],"faster":[122],"advantage":[128],"proposed":[131,177,191],"work":[132],"lies":[133],"directly":[135],"applying":[136],"key":[139],"address,":[142],"helps":[144],"contents":[147],"units.":[150],"CAMs":[151],"literature":[154],"exhaust":[155],"entire":[157],"remapping":[161],"words":[164],"along":[165],"with":[166],"word,":[169],"leads":[171],"higher":[173],"latency.":[175],"implemented":[180],"Virtex-6":[183],"FPGA,":[184],"show":[188],"that":[189],"method":[192],"brings":[193],"latency":[194],"only":[196],"two":[197],"clock":[198],"cycles":[199],"during":[200],"update.":[201]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2022,"cited_by_count":3}],"updated_date":"2026-09-22T06:50:58.402377","created_date":"2021-03-15T00:00:00"}