{"id":"https://openalex.org/W3131907486","doi":"https://doi.org/10.37394/23201.2020.19.32","title":"Investigation on Power, Delay and Area optimization of XOR Gate","display_name":"Investigation on Power, Delay and Area optimization of XOR Gate","publication_year":2021,"publication_date":"2021-02-24","ids":{"openalex":"https://openalex.org/W3131907486","doi":"https://doi.org/10.37394/23201.2020.19.32","mag":"3131907486"},"language":"en","primary_location":{"id":"doi:10.37394/23201.2020.19.32","doi":"https://doi.org/10.37394/23201.2020.19.32","is_oa":true,"landing_page_url":"https://doi.org/10.37394/23201.2020.19.32","pdf_url":"https://doi.org/10.37394/23201.2020.19.32","source":{"id":"https://openalex.org/S2764701073","display_name":"WSEAS Transactions on Circuits and Systems archive","issn_l":"1109-2734","issn":["1109-2734","2224-266X"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","poland-20","russia-white-list-4"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://doi.org/10.37394/23201.2020.19.32","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004332291","display_name":"V. Thamizharasan","orcid":"https://orcid.org/0000-0001-7896-7164","observed_orcids":["https://orcid.org/0000-0001-7896-7164"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Thamizharasan. V","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Erode, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Erode, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053416047","display_name":"M. Ramya","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ramya. M","raw_affiliation_strings":["Erode Sengunthar Engineering College, Perundurai, Erode, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Erode Sengunthar Engineering College, Perundurai, Erode, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":93},"biblio":{"volume":"19","issue":null,"first_page":"297","last_page":"304"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.9980000257492065},{"id":"https://openalex.org/keywords/low-power-design","display_name":"low power design","score":0.699999988079071},{"id":"https://openalex.org/keywords/cmos-layout","display_name":"CMOS layout","score":0.5070000290870667},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"pass transistor logic","score":0.828000009059906},{"id":"https://openalex.org/keywords/transmission-gate","display_name":"transmission gate","score":0.9419999718666077},{"id":"https://openalex.org/keywords/power-consumption","display_name":"power consumption","score":0.6449999809265137},{"id":"https://openalex.org/keywords/reduction-of-area","display_name":"area reduction","score":0.6230000257492065},{"id":"https://openalex.org/keywords/delay-optimization","display_name":"delay optimization","score":0.5889999866485596},{"id":"https://openalex.org/keywords/multiplier-architecture","display_name":"multiplier architecture","score":0.44699999690055847},{"id":"https://openalex.org/keywords/adders","display_name":"adders","score":0.8059999942779541}],"concepts":[{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.9295128583908081},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7251784801483154},{"id":"https://openalex.org/C60697091","wikidata":"https://www.wikidata.org/wiki/Q5527009","display_name":"Gate equivalent","level":5,"score":0.6525614857673645},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6245142817497253},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.563143789768219},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5569869875907898},{"id":"https://openalex.org/C2780949067","wikidata":"https://www.wikidata.org/wiki/Q1136752","display_name":"Transmission gate","level":4,"score":0.5403642058372498},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5265486836433411},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.524036705493927},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5217648148536682},{"id":"https://openalex.org/C58140894","wikidata":"https://www.wikidata.org/wiki/Q560398","display_name":"OR gate","level":4,"score":0.47471892833709717},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.44052380323410034},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.41764581203460693},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3393881022930145},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25531211495399475},{"id":"https://openalex.org/C2361726","wikidata":"https://www.wikidata.org/wiki/Q5527031","display_name":"Gate oxide","level":4,"score":0.22784847021102905},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.37394/23201.2020.19.32","doi":"https://doi.org/10.37394/23201.2020.19.32","is_oa":true,"landing_page_url":"https://doi.org/10.37394/23201.2020.19.32","pdf_url":"https://doi.org/10.37394/23201.2020.19.32","source":{"id":"https://openalex.org/S2764701073","display_name":"WSEAS Transactions on Circuits and Systems archive","issn_l":"1109-2734","issn":["1109-2734","2224-266X"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","poland-20","russia-white-list-4"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.37394/23201.2020.19.32","doi":"https://doi.org/10.37394/23201.2020.19.32","is_oa":true,"landing_page_url":"https://doi.org/10.37394/23201.2020.19.32","pdf_url":"https://doi.org/10.37394/23201.2020.19.32","source":{"id":"https://openalex.org/S2764701073","display_name":"WSEAS Transactions on Circuits and Systems archive","issn_l":"1109-2734","issn":["1109-2734","2224-266X"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","poland-20","russia-white-list-4"],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS","raw_type":"journal-article"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4943999946117401}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3131907486.pdf","grobid_xml":"https://content.openalex.org/works/W3131907486.grobid-xml"},"referenced_works_count":11,"referenced_works":["https://openalex.org/W2086259249","https://openalex.org/W2736841978","https://openalex.org/W2795373693","https://openalex.org/W2803057706","https://openalex.org/W2889877687","https://openalex.org/W2939567942","https://openalex.org/W2941060098","https://openalex.org/W2949250270","https://openalex.org/W3016940091","https://openalex.org/W3174540764","https://openalex.org/W4248348570"],"related_works":["https://openalex.org/W2965755076","https://openalex.org/W2136738282","https://openalex.org/W4407277720","https://openalex.org/W2384229851","https://openalex.org/W100177519","https://openalex.org/W2965246497","https://openalex.org/W2902754131","https://openalex.org/W4239418231","https://openalex.org/W2205836173","https://openalex.org/W2108719777"],"abstract_inverted_index":{"Nowadays":[0],"a":[1,53],"mobile":[2],"computing":[3],"and":[4,13,48,63,110,122],"multimedia":[5],"applications":[6],"are":[7,81],"need":[8],"for":[9],"high-performance":[10],"reduced":[11],"size":[12],"low-power":[14],"devices.":[15],"The":[16,116],"multiplication":[17],"is":[18,31,41],"major":[19,35],"operation":[20],"in":[21,124],"any":[22,27],"signal":[23],"processing":[24,36],"applications.":[25],"In":[26,38,50,68,127],"multiplier":[28],"architecture,":[29],"adder":[30,47],"one":[32],"of":[33,45,57,113,135,142,145,147,155],"the":[34,42,74,77,129],"elements.":[37],"which":[39],"XOR":[40,58,70,83],"basic":[43],"block":[44],"an":[46],"multiplier.":[49],"this":[51],"paper,":[52],"various":[54],"design":[55],"styles":[56],"Gate":[59,97,102,115,157],"have":[60],"been":[61],"surveyed":[62],"simulated":[64,123],"using":[65,76],"Microwind":[66,125],"tool.":[67],"that":[69,128],"gate":[71],"was":[72,120],"analyzed":[73],"power":[75,136],"different":[78],"styles.":[79],"They":[80],"conventional":[82],"gate,":[84,90,95],"Pass":[85],"transistor":[86,148],"logic":[87],"based":[88,93,98,103],"EX-OR":[89,94,99,101,114,156],"Static":[91],"inverter":[92],"Transmission":[96],"Gate,":[100],"on":[104],"8":[105],"&":[106,109],"6":[107],"Transistor":[108],"Modified":[111],"version":[112,154],"CMOS":[117],"circuit":[118,132],"layout":[119],"created":[121],"software.":[126],"proposed":[130],"XOR-based":[131],"has":[133,138],"40.17%":[134],"consumption":[137],"improved":[139,149],"&14.28":[140],"%":[141],"area":[143],"in-terms":[144],"number":[146],"as":[150],"compare":[151],"to":[152],"modified":[153],"design.":[158]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-09-21T07:43:02.447757","created_date":"2021-03-01T00:00:00"}
