{"id":"https://openalex.org/W30928993","doi":null,"title":"Transistor chaining and transistor reordering in the design of CMOS complex gates","display_name":"Transistor chaining and transistor reordering in the design of CMOS complex gates","publication_year":1992,"publication_date":"1992-01-01","ids":{"openalex":"https://openalex.org/W30928993","mag":"30928993"},"language":"en","primary_location":{"id":"mag:30928993","doi":null,"is_oa":false,"landing_page_url":"https://dl.acm.org/citation.cfm?id=144183","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019287169","display_name":"B.S. Carlson","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I70983195","display_name":"Syracuse University","ror":"https://ror.org/025r5qe02","country_code":"US","type":"education","lineage":["https://openalex.org/I70983195"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"B.S. Carlson","raw_affiliation_strings":["Syracuse Univ., Syracuse NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Syracuse Univ., Syracuse NY","institution_ids":["https://openalex.org/I70983195"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5019287169"],"corresponding_institution_ids":["https://openalex.org/I70983195"],"apc_list":null,"apc_paid":null,"fwci":0.4636,"has_fulltext":true,"cited_by_count":7,"citation_normalized_percentile":{"value":0.58013376,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.007699999958276749,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dynamic-cmos","display_name":"dynamic CMOS","score":0.800000011920929},{"id":"https://openalex.org/keywords/static-cmos","display_name":"static CMOS","score":0.984000027179718},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"propagation delay","score":0.8050000071525574},{"id":"https://openalex.org/keywords/heuristic-optimization","display_name":"heuristic optimization","score":0.36500000953674316},{"id":"https://openalex.org/keywords/np-hardness","display_name":"NP-hardness","score":0.6869999766349792}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6742331385612488},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5907111763954163},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.5599410533905029},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5063306093215942},{"id":"https://openalex.org/C173801870","wikidata":"https://www.wikidata.org/wiki/Q201413","display_name":"Heuristic","level":2,"score":0.5045458078384399},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.504097580909729},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4773842692375183},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4273068606853485},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3688478469848633},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34996676445007324},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20860716700553894},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1464889645576477},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11015263199806213},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09101319313049316}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:30928993","doi":null,"is_oa":false,"landing_page_url":"https://dl.acm.org/citation.cfm?id=144183","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[{"id":"https://openalex.org/G6911292808","display_name":"Novel agonist tracers for PET imaging of kappa opioid receptors","funder_award_id":"R21MH092664","funder_id":"https://openalex.org/F4320337346","funder_display_name":"National Institute of Mental Health"},{"id":"https://openalex.org/G7572000859","display_name":"Novel agonist tracers for PET imaging of kappa opioid receptors","funder_award_id":"R33MH092664","funder_id":"https://openalex.org/F4320337346","funder_display_name":"National Institute of Mental Health"},{"id":"https://openalex.org/G9000905448","display_name":"Yale Clinical and Translational Science Award","funder_award_id":"UL1TR001863","funder_id":"https://openalex.org/F4320332161","funder_display_name":"National Institutes of Health"}],"funders":[{"id":"https://openalex.org/F4320332161","display_name":"National Institutes of Health","ror":"https://ror.org/01cwqze88"},{"id":"https://openalex.org/F4320337346","display_name":"National Institute of Mental Health","ror":"https://ror.org/04xeg9z08"},{"id":"https://openalex.org/F4320337472","display_name":"National Center for Advancing Translational Sciences","ror":"https://ror.org/04pw6fb54"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":37,"referenced_works":["https://openalex.org/W961370287","https://openalex.org/W1590451711","https://openalex.org/W1660439970","https://openalex.org/W1829470622","https://openalex.org/W1922688499","https://openalex.org/W1938163261","https://openalex.org/W1967288063","https://openalex.org/W1969593376","https://openalex.org/W1983754627","https://openalex.org/W1993136139","https://openalex.org/W2014786081","https://openalex.org/W2018453129","https://openalex.org/W2036600146","https://openalex.org/W2053012680","https://openalex.org/W2058046532","https://openalex.org/W2064450732","https://openalex.org/W2081153295","https://openalex.org/W2086917529","https://openalex.org/W2095299275","https://openalex.org/W2116874726","https://openalex.org/W2121435283","https://openalex.org/W2134366865","https://openalex.org/W2156876729","https://openalex.org/W2167295928","https://openalex.org/W2253007843","https://openalex.org/W2261568414","https://openalex.org/W2261682839","https://openalex.org/W2312759843","https://openalex.org/W2462643901","https://openalex.org/W2534384157","https://openalex.org/W2557283477","https://openalex.org/W2572571751","https://openalex.org/W2741288947","https://openalex.org/W2755924589","https://openalex.org/W2901794162","https://openalex.org/W7067800696","https://openalex.org/W7074234824"],"related_works":["https://openalex.org/W2171874034","https://openalex.org/W2111085901","https://openalex.org/W2125566804","https://openalex.org/W2118951767","https://openalex.org/W1844420817","https://openalex.org/W7099747492","https://openalex.org/W2169652762","https://openalex.org/W2156636175","https://openalex.org/W2069959892","https://openalex.org/W2087118030"],"abstract_inverted_index":{"The":[0,14,107,126,154,209],"problem":[1,111],"of":[2,8,38,43,52,71,80,94,135,138,150,185,193,203,215,226,241,272,278,323],"chaining":[3],"transistors":[4,139,186,230,259],"in":[5,104,133,140,147,187,231,238,250,260,311],"the":[6,36,39,44,47,69,72,77,91,136,141,151,188,200,227,239,258,269,273,291,301,321,324],"layout":[7,30,33,63,66,110,160,192,242,309],"CMOS":[9,54,82,233],"complex":[10,55,83,217,234],"gates":[11],"is":[12,31,41,64,74,102,115,121,175,207,254,281,284],"addressed.":[13],"layouts":[15,95,253],"are":[16],"partitioned":[17],"into":[18],"two":[19,92,177],"classes;":[20],"namely,":[21],"dual":[22,25,28,61,78,108,158,251],"independent":[23,29,42,159,252],"and":[24,49,97,143,190,221,244],"dependent.":[26],"A":[27,60],"a":[32,53,65,81,163,176,191,212,216,223,232,245,261,265,275,297],"for":[34,67,90,100,112,123,157,167,247,287],"which":[35,68,180,198],"optimality":[37,70],"solution":[40,73],"duality":[45],"between":[46],"PMOS":[48],"NMOS":[50],"networks":[51],"gate":[56,84,218,235,262],"(e.g.,":[57,85],"dynamic":[58],"CMOS).":[59,87],"dependent":[62,75,109],"on":[76,268,300,320],"property":[79],"static":[86],"Optimization":[88],"algorithms":[89],"classes":[93],"differ,":[96],"one":[98],"algorithm":[99,128,155,179,197,210],"each":[101],"presented":[103,156],"this":[105,249,279],"dissertation.":[106],"non-series/parallel":[113,168],"circuits":[114,169,290],"NP-hard;":[116],"therefore,":[117,304],"an":[118,182,204,317],"efficient":[119],"heuristic":[120,127],"proposed":[122],"its":[124],"solution.":[125],"has":[129],"linear":[130],"time":[131],"complexity":[132],"terms":[134],"number":[137],"circuit,":[142,189,274],"produces":[144,222],"optimal":[145,183],"solutions":[146],"92":[148],"percent":[149],"test":[152],"cases.":[153],"generation":[161],"utilizes":[162],"new":[164],"tree":[165,201,224],"representation":[166,202,225],"to":[170,307],"perform":[171],"transistor":[172,292,305],"reordering.":[173],"It":[174,283],"stage":[178],"determines":[181,199],"reordering":[184,257,306],"optimum":[194],"width.":[195],"An":[196],"arbitrary":[205],"circuit":[206],"presented.":[208,255],"accepts":[211],"SPICE":[213],"description":[214],"as":[219],"input,":[220],"circuit.":[228,325],"Reordering":[229],"can":[236],"result":[237],"reduction":[240],"area,":[243],"technique":[246],"doing":[248],"Since":[256],"may":[263],"have":[264,296,316],"significant":[266,298],"effect":[267,280,299,319],"timing":[270],"behavior":[271],"simulation-based":[276],"investigation":[277],"performed.":[282],"shown":[285],"that":[286],"many":[288],"practical":[289],"order":[293],"does":[294,314],"not":[295,315],"propagation":[302],"delay;":[303],"decrease":[308],"area":[310],"most":[312],"cases":[313],"adverse":[318],"design":[322]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2016-06-24T00:00:00"}
