{"id":"https://openalex.org/W3087937571","doi":"https://doi.org/10.1049/iet-cdt.2019.0090","title":"Towards IP integration on SoC: a case study of high\u2010throughput and low\u2010cost wrapper design on a novel IBUS architecture","display_name":"Towards IP integration on SoC: a case study of high\u2010throughput and low\u2010cost wrapper design on a novel IBUS architecture","publication_year":2020,"publication_date":"2020-09-18","ids":{"openalex":"https://openalex.org/W3087937571","doi":"https://doi.org/10.1049/iet-cdt.2019.0090","mag":"3087937571"},"language":"en","primary_location":{"id":"doi:10.1049/iet-cdt.2019.0090","doi":"https://doi.org/10.1049/iet-cdt.2019.0090","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt.2019.0090","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"listed_in":["cwts-core","doaj","dongbi-c","jufo-1","norway-1","oarl","poland-70","russia-white-list-3"],"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers & Digital Techniques","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058511319","display_name":"Xiaokun Yang","orcid":"https://orcid.org/0000-0002-1236-6857","observed_orcids":["https://orcid.org/0000-0002-1236-6857"]},"institutions":[{"id":"https://openalex.org/I52913039","display_name":"University of Houston - Clear Lake","ror":"https://ror.org/01t817z14","country_code":"US","type":"education","lineage":["https://openalex.org/I52913039"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xiaokun Yang","raw_affiliation_strings":["Engineering Department, University of Houston Clear Lake, Houston, TX, 77058 USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Engineering Department, University of Houston Clear Lake, Houston, TX, 77058 USA","institution_ids":["https://openalex.org/I52913039"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072283764","display_name":"Shi Sha","orcid":"https://orcid.org/0000-0002-5182-9666","observed_orcids":["https://orcid.org/0000-0002-5182-9666"]},"institutions":[{"id":"https://openalex.org/I160003610","display_name":"Wilkes University","ror":"https://ror.org/054nntz49","country_code":"US","type":"education","lineage":["https://openalex.org/I160003610"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shi Sha","raw_affiliation_strings":["Department of Electrical Engineering, Wilkes University, Wilkes-Barre, PA, 18766 USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Wilkes University, Wilkes-Barre, PA, 18766 USA","institution_ids":["https://openalex.org/I160003610"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040529624","display_name":"Ishaq Unwala","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I52913039","display_name":"University of Houston - Clear Lake","ror":"https://ror.org/01t817z14","country_code":"US","type":"education","lineage":["https://openalex.org/I52913039"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ishaq Unwala","raw_affiliation_strings":["Engineering Department, University of Houston Clear Lake, Houston, TX, 77058 USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Engineering Department, University of Houston Clear Lake, Houston, TX, 77058 USA","institution_ids":["https://openalex.org/I52913039"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101926743","display_name":"Jiang Lu","orcid":"https://orcid.org/0000-0003-3199-5939","observed_orcids":["https://orcid.org/0000-0003-3199-5939"]},"institutions":[{"id":"https://openalex.org/I52913039","display_name":"University of Houston - Clear Lake","ror":"https://ror.org/01t817z14","country_code":"US","type":"education","lineage":["https://openalex.org/I52913039"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jiang Lu","raw_affiliation_strings":["Engineering Department, University of Houston Clear Lake, Houston, TX, 77058 USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Engineering Department, University of Houston Clear Lake, Houston, TX, 77058 USA","institution_ids":["https://openalex.org/I52913039"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5058511319"],"corresponding_institution_ids":["https://openalex.org/I52913039"],"apc_list":{"value":2210,"currency":"USD","value_usd":2210},"apc_paid":null,"fwci":0.2003,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.51611842,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":93},"biblio":{"volume":"14","issue":"6","first_page":"353","last_page":"362"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9223999977111816,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9223999977111816,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.04190000146627426,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.032499998807907104,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/system-on-chip","display_name":"system-on-chip","score":0.9660000205039978},{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.8360000252723694},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"energy consumption","score":0.9589999914169312},{"id":"https://openalex.org/keywords/data-throughput","display_name":"data throughput","score":0.6570000052452087},{"id":"https://openalex.org/keywords/verification-ip","display_name":"verification IP","score":0.5339999794960022},{"id":"https://openalex.org/keywords/block-cipher","display_name":"block cipher","score":0.3569999933242798},{"id":"https://openalex.org/keywords/block-test","display_name":"block test","score":0.32499998807907104}],"concepts":[{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.7337075471878052},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7264350652694702},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6246851086616516},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5302512049674988},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5154522061347961},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.44484949111938477},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1059243381023407},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1049/iet-cdt.2019.0090","doi":"https://doi.org/10.1049/iet-cdt.2019.0090","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cdt.2019.0090","pdf_url":null,"source":{"id":"https://openalex.org/S28293273","display_name":"IET Computers & Digital Techniques","issn_l":"1751-8601","issn":["1751-8601","1751-861X"],"is_oa":false,"is_in_doaj":true,"is_core":true,"listed_in":["cwts-core","doaj","dongbi-c","jufo-1","norway-1","oarl","poland-70","russia-white-list-3"],"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Computers & Digital Techniques","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.8970999717712402,"display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1427117215","https://openalex.org/W1986199539","https://openalex.org/W2029460293","https://openalex.org/W2033139357","https://openalex.org/W2143968372","https://openalex.org/W2310941977","https://openalex.org/W2532719504","https://openalex.org/W2543034682","https://openalex.org/W2581963379","https://openalex.org/W2588125506","https://openalex.org/W2613091199","https://openalex.org/W2757349764","https://openalex.org/W2772670724","https://openalex.org/W2784229058","https://openalex.org/W2883405144","https://openalex.org/W2945577986","https://openalex.org/W3036715599","https://openalex.org/W4239981747","https://openalex.org/W4243403952"],"related_works":["https://openalex.org/W2033139357","https://openalex.org/W1518230963","https://openalex.org/W1540403741","https://openalex.org/W2031621863","https://openalex.org/W2972883671","https://openalex.org/W7030487016","https://openalex.org/W2107417310","https://openalex.org/W1643993243","https://openalex.org/W176204149","https://openalex.org/W7097208055"],"abstract_inverted_index":{"To":[0],"integrate":[1],"third\u2010party":[2],"intellectual":[3],"properties":[4],"(IPs)":[5],"into":[6,41,88],"a":[7,13,21,33,73,100,127],"new":[8,22],"system\u2010on\u2010chip":[9],"(SoC)":[10],"architecture":[11],"is":[12,43],"big":[14],"challenge.":[15],"Therefore,":[16],"this":[17],"study":[18],"first":[19],"presents":[20],"bus":[23,28,35,53,66],"protocol":[24],"named":[25],"as":[26,124,126],"integrated":[27],"(IBUS),":[29],"and":[30,55,69,110,139,156],"more":[31],"important,":[32],"configurable":[34],"wrapper":[36],"for":[37,82],"connecting":[38],"AXI3\u2010interfaced":[39,85],"IPs":[40,87],"IBUS":[42,80,90],"further":[44],"proposed,":[45],"aiming":[46],"to":[47],"finding":[48],"the":[49,76,107,112,117,131,136,142,147],"optimal":[50],"balance":[51],"between":[52],"efficiency":[54],"resource":[56],"cost":[57],"in":[58,106,111,130,135,141],"terms":[59],"of":[60,150],"field\u2010programming":[61],"gate":[62],"array":[63],"slice":[64,151],"count,":[65],"transfer":[67,154],"latency,":[68,155],"energy":[70,157],"consumption.":[71],"As":[72],"case":[74],"study,":[75],"authors":[77],"implemented":[78],"three":[79,84],"wrappers":[81],"integrating":[83],"verification":[86],"an":[89],"SoC.":[91],"Experimental":[92],"results":[93],"show":[94],"that":[95],"their":[96],"proposed":[97],"work":[98],"achieves":[99],"higher":[101],"valid":[102],"data":[103,153],"throughput":[104],"(":[105],"block":[108,137],"test":[109],"cipher":[113,143],"test)":[114],"compared":[115],"with":[116],"designs":[118],"on":[119],"conventional":[120],"bridge\u2010based":[121],"SoC":[122],"integration,":[123],"well":[125],"large":[128],"reduction":[129],"normalised":[132],"slice\u2010time\u2010power":[133],"(18.73%":[134],"benchmark":[138],"23.45%":[140],"benchmark)":[144],"when":[145],"setting":[146],"same":[148],"weights":[149],"number,":[152],"dissipation.":[158]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-11-13T13:42:25.865203","created_date":"2020-10-01T00:00:00"}