{"id":"https://openalex.org/W3009248010","doi":null,"title":"Ferramentas para gera\u00e7\u00e3o autom\u00e1tica de aceleradores em plataformas heterog\u00eaneas de alto desempenho com FPGA","display_name":"Ferramentas para gera\u00e7\u00e3o autom\u00e1tica de aceleradores em plataformas heterog\u00eaneas de alto desempenho com FPGA","publication_year":2018,"publication_date":"2018-07-27","ids":{"openalex":"https://openalex.org/W3009248010","mag":"3009248010"},"language":"pt","primary_location":{"id":"pmh:oai:locus.ufv.br:123456789/27614","doi":null,"is_oa":true,"landing_page_url":"https://locus.ufv.br//handle/123456789/27614","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"instacron:UFV","raw_type":"info:eu-repo/semantics/masterThesis"},"volume":null,"type":"dissertation","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://locus.ufv.br//handle/123456789/27614","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034643755","display_name":"Jeronimo Costa Penha","orcid":"https://orcid.org/0000-0002-8422-1999","observed_orcids":["https://orcid.org/0000-0002-8422-1999"]},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Jeronimo Costa Penha","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0002-8422-1999","affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":["https://openalex.org/A5034643755"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.0006000000284984708,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0006000000284984708,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.6389999985694885},{"id":"https://openalex.org/keywords/data-flow-graphs","display_name":"data flow graphs","score":0.8080000281333923},{"id":"https://openalex.org/keywords/k-means-clustering","display_name":"K-means clustering","score":0.7540000081062317},{"id":"https://openalex.org/keywords/gpu-acceleration","display_name":"GPU acceleration","score":0.8629999756813049},{"id":"https://openalex.org/keywords/opencl","display_name":"OpenCL","score":0.6079999804496765},{"id":"https://openalex.org/keywords/energy-efficiency","display_name":"energy efficiency","score":0.703000009059906},{"id":"https://openalex.org/keywords/high-performance-computing","display_name":"high-performance computing","score":0.7799999713897705}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6004624962806702},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44304850697517395},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2528620958328247}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:locus.ufv.br:123456789/27614","doi":null,"is_oa":true,"landing_page_url":"https://locus.ufv.br//handle/123456789/27614","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"instacron:UFV","raw_type":"info:eu-repo/semantics/masterThesis"},{"id":"mag:3009248010","doi":null,"is_oa":false,"landing_page_url":"https://www.locus.ufv.br/handle/123456789/27614","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":{"id":"pmh:oai:locus.ufv.br:123456789/27614","doi":null,"is_oa":true,"landing_page_url":"https://locus.ufv.br//handle/123456789/27614","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"instacron:UFV","raw_type":"info:eu-repo/semantics/masterThesis"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.8970999717712402,"id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4406985388","https://openalex.org/W7120587713","https://openalex.org/W2579553654","https://openalex.org/W4206065067","https://openalex.org/W4392313774","https://openalex.org/W2402675130","https://openalex.org/W3008897664","https://openalex.org/W7130561387","https://openalex.org/W643552430","https://openalex.org/W2559355536"],"abstract_inverted_index":{"A":[0,169,196,225],"era":[1],"Big":[2],"Data":[3],"e":[4,48,90,100,124,157,165,191,255,266,281],"a":[5,81,110,136,150,241],"estagna\u00e7\u00e3o":[6],"da":[7,138,270],"evolu\u00e7\u00e3o":[8],"dos":[9,193],"processadores":[10,156],"devido":[11,80],"aos":[12],"desafios":[13],"de":[14,20,23,35,55,63,65,68,84,88,92,94,108,112,120,122,129,142,147,167,175,177,181,183,207,211,220,272,279],"efici\u00eancia":[15,59,282],"energ\u00e9tica,":[16],"motiva":[17],"o":[18,28,106,127,216,229,268],"surgimento":[19],"novas":[21],"arquiteturas":[22,43,153,194],"dom\u00ednios":[24],"espec\u00edficos":[25],"buscando":[26],"aumentar":[27],"desempenho.":[29],"Juntamente":[30],"ao":[31],"desenvolvimento":[32,89,128,141,164,176],"das":[33,243],"placas":[34],"v\u00eddeo":[36],"(Graphics":[37],"Processing":[38],"Unit":[39],"-":[40],"GPU":[41],"),":[42],"h\u00edbridas":[44],"CPU-FPGA":[45,237],"tem":[46,133],"surgido":[47],"demonstrado":[49],"potencial":[50,269],"para":[51,61,126,149,163,204,231,240],"utiliza\u00e7\u00e3o":[52,271],"em":[53,145,152,223,233],"computa\u00e7\u00e3o":[54],"alto":[56],"desempenho":[57],"com":[58,105,155,179,215,274],"energ\u00e9tica":[60],"processamento":[62],"fluxo":[64,146,182],"dados.":[66],"Apesar":[67],"serem":[69],"promissores,":[70],"os":[71,115],"FPGAs":[72,116],"(Field-Programmable":[73],"Gate":[74],"Array)":[75],"ainda":[76,117],"s\u00e3o":[77],"pouco":[78],"utilizados":[79],"baixa":[82],"velocidade":[83],"chaveamento":[85],"(clock),":[86],"complexidade":[87,111,139],"taxas":[91],"transfer\u00eancia":[93],"dados":[95,148,184],"limitadas.":[96],"Ferramentas,":[97],"como":[98,134],"OpenSPL":[99],"OpenCL,":[101],"t\u00eam":[102],"sido":[103],"desenvolvidas":[104,249,263],"objetivo":[107,135],"reduzir":[109],"desenvolvimento.":[113],"Por\u00e9m,":[114],"requerem":[118],"conhecimento":[119],"arquitetura":[121],"computadores":[123],"hardware":[125],"solu\u00e7\u00f5es.":[130],"Este":[131],"trabalho":[132],"redu\u00e7\u00e3o":[137],"no":[140,187],"algoritmos":[143,178],"baseados":[144],"execu\u00e7\u00e3o":[151,166,192,232,280],"heterog\u00eaneas":[154],"FPGAs.":[158],"S\u00e3o":[159],"propostas":[160],"duas":[161],"ferramentas":[162,262],"algoritmos.":[168],"primeira,":[170],"\u201cADD\u201d,":[171],"\u00e9":[172,199],"uma":[173],"ferramenta":[174,198,226],"grafos":[180],"que":[185],"auxilia":[186],"projeto,":[188],"simula\u00e7\u00e3o,":[189],"gera\u00e7\u00e3o":[190],"desenvolvidas.":[195],"segunda":[197],"um":[200,205],"gerador":[201],"autom\u00e1tico":[202],"espec\u00edfico":[203],"dom\u00ednio":[206],"classifica\u00e7\u00e3o":[208],"n\u00e3o":[209],"supervisionada":[210],"da-":[212],"dos,":[213],"implementada":[214],"algoritmo":[217],"K-means":[218,230],"capaz":[219],"gerar":[221],"solu\u00e7\u00f5es":[222],"FPGA.":[224],"gera":[227],"tamb\u00e9m":[228],"GPU.":[234],"Duas":[235],"plataformas":[236,247],"foram":[238,248,264],"utilizadas":[239],"valida\u00e7\u00e3o":[242],"ferramentas.":[244],"Ambas":[245],"as":[246],"pela":[250],"Altera/Intel,":[251],"denominadas":[252],"HARP":[253,256],"1":[254],"2.":[257],"Os":[258],"resultados":[259],"obtidos":[260],"pelas":[261],"promissores":[265],"mostram":[267],"aceleradores":[273],"FPGA":[275],"nos":[276],"quesitos":[277],"tempos":[278],"energ\u00e9tica.":[283]},"counts_by_year":[],"updated_date":"2026-11-08T12:12:28.789561","created_date":"2020-03-13T00:00:00"}
