{"id":"https://openalex.org/W2977415399","doi":"https://doi.org/10.1109/async.2019.00012","title":"A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET","display_name":"A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2977415399","doi":"https://doi.org/10.1109/async.2019.00012","mag":"2977415399"},"language":"en","primary_location":{"id":"doi:10.1109/async.2019.00012","doi":"https://doi.org/10.1109/async.2019.00012","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2019.00012","pdf_url":null,"source":{"id":"https://openalex.org/S4210190146","display_name":"IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","issn_l":"1522-8681","issn":["1522-8681"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087082539","display_name":"Matthew R. Fojtik","orcid":"https://orcid.org/0000-0003-3138-9293","observed_orcids":["https://orcid.org/0000-0003-3138-9293"]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew Fojtik","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001800455","display_name":"Ben Keller","orcid":"https://orcid.org/0000-0002-8117-1412","observed_orcids":["https://orcid.org/0000-0002-8117-1412"]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ben Keller","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009735174","display_name":"Alicia Klinefelter","orcid":"https://orcid.org/0000-0002-0149-0393","observed_orcids":["https://orcid.org/0000-0002-0149-0393"]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alicia Klinefelter","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050270997","display_name":"Nathaniel Pinckney","orcid":"https://orcid.org/0000-0001-6159-8964","observed_orcids":["https://orcid.org/0000-0001-6159-8964"]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nathaniel Pinckney","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102966476","display_name":"Stephen G. Tell","orcid":"https://orcid.org/0000-0002-2166-1452","observed_orcids":["https://orcid.org/0000-0002-2166-1452"]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen G. Tell","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042467215","display_name":"Brian Zimmer","orcid":"https://orcid.org/0000-0001-9997-3141","observed_orcids":["https://orcid.org/0000-0001-9997-3141"]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brian Zimmer","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108401339","display_name":"Tezaswi Raja","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tezaswi Raja","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Kevin Zhou","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin Zhou","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007028607","display_name":"W.J. Dally","orcid":"https://orcid.org/0000-0003-4632-2876","observed_orcids":["https://orcid.org/0000-0003-4632-2876"]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"William J. Dally","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010156116","display_name":"Brucek Khailany","orcid":"https://orcid.org/0000-0002-7584-3489","observed_orcids":["https://orcid.org/0000-0002-7584-3489"]},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Brucek Khailany","raw_affiliation_strings":["NVIDIA Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NVIDIA Corporation","institution_ids":["https://openalex.org/I4210127875"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210127875"],"apc_list":null,"apc_paid":null,"fwci":3.5643,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.94139634,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":88,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"27","last_page":"35"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.5425000190734863,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.5425000190734863,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.23229999840259552,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.11990000307559967,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/globally-asynchronous-locally-synchronous","display_name":"globally asynchronous locally synchronous","score":0.8460000157356262},{"id":"https://openalex.org/keywords/adaptive-clocking","display_name":"adaptive clocking","score":0.8809999823570251},{"id":"https://openalex.org/keywords/power-supply-noise","display_name":"power supply noise","score":0.8960000276565552},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"clock domain crossing","score":0.8460000157356262},{"id":"https://openalex.org/keywords/network-on-chip","display_name":"network-on-chip","score":0.6759999990463257},{"id":"https://openalex.org/keywords/16-nm-finfet","display_name":"16nm FinFET","score":0.8330000042915344},{"id":"https://openalex.org/keywords/low-voltage-operation","display_name":"low-voltage operation","score":0.5699999928474426},{"id":"https://openalex.org/keywords/energy-efficiency","display_name":"energy efficiency","score":0.5130000114440918},{"id":"https://openalex.org/keywords/timing-margin","display_name":"timing margin","score":0.5410000085830688}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.7694145441055298},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7255578637123108},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6012179255485535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5071680545806885},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.49660903215408325},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.46519505977630615},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.44835904240608215},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.41394859552383423},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39382869005203247},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3327729403972626},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17457294464111328},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10247024893760681},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/async.2019.00012","doi":"https://doi.org/10.1109/async.2019.00012","is_oa":false,"landing_page_url":"https://doi.org/10.1109/async.2019.00012","pdf_url":null,"source":{"id":"https://openalex.org/S4210190146","display_name":"IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","issn_l":"1522-8681","issn":["1522-8681"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5378999710083008,"id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1571295343","https://openalex.org/W1609287256","https://openalex.org/W1652623996","https://openalex.org/W1666015432","https://openalex.org/W1943426535","https://openalex.org/W1951447215","https://openalex.org/W1964330375","https://openalex.org/W1978760319","https://openalex.org/W1981384041","https://openalex.org/W2032252505","https://openalex.org/W2051192488","https://openalex.org/W2101456474","https://openalex.org/W2133079932","https://openalex.org/W2139349254","https://openalex.org/W2150415477","https://openalex.org/W2158815563","https://openalex.org/W2528504743","https://openalex.org/W2529252381","https://openalex.org/W2591632264","https://openalex.org/W2594523692","https://openalex.org/W2594678906","https://openalex.org/W2610603505","https://openalex.org/W2737123894","https://openalex.org/W2791679455","https://openalex.org/W2798724095","https://openalex.org/W2808932028","https://openalex.org/W6734752540","https://openalex.org/W6748888857"],"related_works":["https://openalex.org/W2529252381","https://openalex.org/W2131308327","https://openalex.org/W2162773063","https://openalex.org/W2910870562","https://openalex.org/W2100656006","https://openalex.org/W2292232352","https://openalex.org/W4254596596","https://openalex.org/W1511690374","https://openalex.org/W2440662882","https://openalex.org/W2036486486"],"abstract_inverted_index":{"Modern":[0],"SoCs":[1],"suffer":[2],"from":[3],"power":[4,30,73],"supply":[5,31,74],"noise":[6],"that":[7],"can":[8,25],"require":[9],"significant":[10],"additional":[11],"timing":[12,45],"margin,":[13],"reducing":[14],"performance":[15,82],"and":[16,71,119],"energy":[17],"efficiency.":[18],"Globally":[19],"asynchronous,":[20],"locally":[21],"synchronous":[22],"(GALS)":[23],"systems":[24],"mitigate":[26,72],"the":[27,41,84,122],"impact":[28],"of":[29,116,125],"noise,":[32,75],"as":[33,35],"well":[34],"simplify":[36],"system":[37],"design":[38],"by":[39],"removing":[40],"need":[42],"for":[43,130],"global":[44,97],"closure.":[46],"This":[47],"work":[48],"presents":[49],"a":[50,62,78,89,113],"4mm2":[51],"distributed":[52],"accelerator":[53],"engine":[54],"with":[55],"19":[56],"independent":[57],"clock":[58,67,105],"domains":[59],"implemented":[60],"in":[61,77,81],"16nm":[63],"process.":[64],"Local":[65],"adaptive":[66],"generators":[68],"dynamically":[69],"tolerate":[70],"resulting":[76],"10%":[79],"improvement":[80],"at":[83],"same":[85],"voltage":[86],"compared":[87],"to":[88],"globally-clocked":[90],"baseline.":[91],"Pausible":[92],"bisynchronous":[93],"FIFOs":[94],"enable":[95],"low-latency":[96],"communication":[98],"across":[99,112],"an":[100],"onchip":[101],"network":[102],"via":[103],"error-free":[104],"domain":[106],"crossings.":[107],"The":[108],"SoC":[109,132],"functions":[110],"robustly":[111],"wide":[114],"range":[115],"voltages,":[117],"frequencies,":[118],"workloads,":[120],"demonstrating":[121],"practical":[123],"applicability":[124],"fine":[126],"grained":[127],"GALS":[128],"techniques":[129],"modern":[131],"design.":[133]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":1}],"updated_date":"2026-10-27T15:51:10.671819","created_date":"2019-10-10T00:00:00"}