{"id":"https://openalex.org/W2974997014","doi":null,"title":"Design and Evaluation of Dynamically Specialized Datapaths with the DySER Architecture","display_name":"Design and Evaluation of Dynamically Specialized Datapaths with the DySER Architecture","publication_year":2010,"publication_date":"2010-01-01","ids":{"openalex":"https://openalex.org/W2974997014","mag":"2974997014"},"language":"en","primary_location":{"id":"pmh:oai:minds.wisc.edu:1793/60724","doi":null,"is_oa":true,"landing_page_url":"http://digital.library.wisc.edu/1793/60724","pdf_url":"https://minds.wisc.edu/bitstreams/c6f354bd-c639-49e2-ba0a-15d8771f5146/download","source":{"id":"https://openalex.org/S4306401622","display_name":"Minds at UW (University of Wisconsin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I135310074","host_organization_name":"University of Wisconsin\u2013Madison","host_organization_lineage":["https://openalex.org/I135310074"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Technical Report"},"volume":null,"type":"report","is_traditional":false,"indexed_in":[],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://minds.wisc.edu/bitstreams/c6f354bd-c639-49e2-ba0a-15d8771f5146/download","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076157365","display_name":"Venkatraman Govindaraju","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Venkatraman Govindaraju","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032872832","display_name":"Chen-Han Ho","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chen-Han Ho","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5028943049","display_name":"Karthikeyan Sankaralingam","orcid":"https://orcid.org/0000-0002-8315-2389","observed_orcids":["https://orcid.org/0000-0002-8315-2389"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Karthikeyan Sankaralingam","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0002-8315-2389","affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.6064000129699707,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.6064000129699707,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.3073999881744385,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.03180000185966492,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/code-specialization","display_name":"code specialization","score":0.31200000643730164},{"id":"https://openalex.org/keywords/out-of-order-processors","display_name":"out-of-order processors","score":0.5730000138282776},{"id":"https://openalex.org/keywords/energy-performance-tradeoff","display_name":"energy-performance trade-off","score":0.5929999947547913}],"concepts":[{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6620107889175415},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.535197377204895},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5175284743309021},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3702256381511688},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.14811760187149048},{"id":"https://openalex.org/C166957645","wikidata":"https://www.wikidata.org/wiki/Q23498","display_name":"Archaeology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"pmh:oai:minds.wisc.edu:1793/60724","doi":null,"is_oa":true,"landing_page_url":"http://digital.library.wisc.edu/1793/60724","pdf_url":"https://minds.wisc.edu/bitstreams/c6f354bd-c639-49e2-ba0a-15d8771f5146/download","source":{"id":"https://openalex.org/S4306401622","display_name":"Minds at UW (University of Wisconsin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I135310074","host_organization_name":"University of Wisconsin\u2013Madison","host_organization_lineage":["https://openalex.org/I135310074"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Technical Report"},{"id":"mag:2974997014","doi":null,"is_oa":false,"landing_page_url":"https://minds.wisconsin.edu/handle/1793/60724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":{"id":"pmh:oai:minds.wisc.edu:1793/60724","doi":null,"is_oa":true,"landing_page_url":"http://digital.library.wisc.edu/1793/60724","pdf_url":"https://minds.wisc.edu/bitstreams/c6f354bd-c639-49e2-ba0a-15d8771f5146/download","source":{"id":"https://openalex.org/S4306401622","display_name":"Minds at UW (University of Wisconsin)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I135310074","host_organization_name":"University of Wisconsin\u2013Madison","host_organization_lineage":["https://openalex.org/I135310074"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Technical Report"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5378999710083008,"id":"https://metadata.un.org/sdg/9"}],"study_designs":[],"awards":[{"id":"https://openalex.org/G1288227591","display_name":"CAREER: A Vertically Integrated Approach to Microprocessor Design for Unpredictable Silicon","funder_award_id":"0845751","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G5882298937","display_name":"SHF: Small: Multi-Core Architecture, Applications, and Tools Co-Design","funder_award_id":"0917238","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"},{"id":"https://openalex.org/G6176670391","display_name":"NeTS:Small:A Unified Lookup Framework to Enable the Rapid Deployment of New Protocols in High-Speed Routers","funder_award_id":"0917213","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2974997014.pdf","grobid_xml":"https://content.openalex.org/works/W2974997014.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2130408605","https://openalex.org/W7096218623","https://openalex.org/W2045995930","https://openalex.org/W2901648395","https://openalex.org/W1969529818","https://openalex.org/W2907568758","https://openalex.org/W2908063716","https://openalex.org/W2899763397","https://openalex.org/W7099925739","https://openalex.org/W2905353199"],"abstract_inverted_index":{"Due":[0],"to":[1,44,89,110,178,212,237,247],"limits":[2],"in":[3,13,66,184],"technology":[4,132],"scaling,":[5],"energy":[6,35,47,242,251],"efficiency":[7,36,48],"of":[8,25,31,49,57,78,99,214,234,244],"logic":[9],"devices":[10],"is":[11,257],"decreasing":[12],"successive":[14],"generations.":[15],"To":[16],"provide":[17,230],"continued":[18],"performance":[19,194,255],"improvements":[20],"without":[21],"increasing":[22],"power,":[23],"regardless":[24],"the":[26,32,46,61,82,141,157,165,192,215],"sequential":[27],"or":[28],"parallel":[29],"nature":[30],"application,":[33],"microarchitectural":[34],"must":[37],"improve.":[38],"We":[39],"propose":[40],"Dynamically":[41],"Specialized":[42],"Execution":[43],"improve":[45],"general":[50],"purpose":[51],"programmable":[52],"processors.":[53],"The":[54],"key":[55],"insights":[56],"this":[58],"work":[59],"are":[60],"following.":[62],"First,":[63],"applications":[64],"execute":[65,152],"phases":[67,70],"and":[68,150,163,168,239,249],"these":[69,90],"can":[71,92,116,151,190,209],"be":[72,93,117],"determined":[73],"by":[74,95],"creating":[75],"a":[76,97,104,121,135,145,199,223],"path-tree":[77],"basic-blocks":[79],"rooted":[80],"at":[81,153],"inner-most":[83],"loop.":[84],"Second,":[85],"specialized":[86,200],"datapaths":[87],"corresponding":[88],"path-trees":[91,162],"constructed":[94],"interconnecting":[96],"set":[98],"heterogeneous":[100],"computation":[101],"units":[102],"with":[103,120,222],"circuit-switched":[105],"network,":[106],"which":[107],"we":[108,160],"refer":[109],"as":[111,144,197],"DySER":[112,137,188,207,228],"blocks.":[113],"These":[114],"blocks":[115,189,229],"easily":[118],"integrated":[119,221],"conventional":[122],"processor.":[123],"A":[124,205],"synthesized":[125],"RTL":[126],"implementation":[127],"using":[128,172],"an":[129],"industry":[130],"55nm":[131],"library":[133],"shows":[134],"64-functional-unit":[136],"block":[138,201,208],"occupies":[139],"approximately":[140],"same":[142,193],"area":[143],"64":[146],"KB":[147],"single-ported":[148],"SRAM":[149],"2":[154],"GHz.":[155],"Using":[156],"GCC":[158],"compiler,":[159],"identify":[161],"evaluate":[164],"PARSEC,":[166],"SPEC":[167],"Parboil":[169],"benchmarks":[170],"suites,":[171],"our":[173],"extensions":[174],"for":[175,202],"mapping":[176],"code":[177],"DySER.":[179],"Our":[180],"results":[181],"show":[182],"that":[183],"most":[185],"cases":[186],"two":[187,227],"achieve":[191],"(within":[195],"5%)":[196],"having":[198],"each":[203],"path-tree.":[204],"64-FU":[206],"cover":[210],"12%":[211],"100%":[213],"dynamically":[216],"executed":[217],"instruction":[218],"stream.":[219],"When":[220],"dual-issue":[224],"out-of-order":[225],"processor,":[226],"geometric":[231,240],"mean":[232,241],"speedup":[233],"2.1X":[235],"(1.15X":[236],"10X),":[238],"reduction":[243,252],"40%":[245],"(up":[246],"70%),":[248],"60%":[250],"if":[253],"no":[254],"improvement":[256],"required.":[258]},"counts_by_year":[],"updated_date":"2026-09-12T09:15:50.089291","created_date":"2019-10-03T00:00:00"}
