{"id":"https://openalex.org/W2945527037","doi":"https://doi.org/10.1002/cta.2648","title":"A new structure of three\u2010phase five\u2010level inverter with nested two\u2010level cells","display_name":"A new structure of three\u2010phase five\u2010level inverter with nested two\u2010level cells","publication_year":2019,"publication_date":"2019-05-21","ids":{"openalex":"https://openalex.org/W2945527037","doi":"https://doi.org/10.1002/cta.2648","mag":"2945527037"},"language":"en","primary_location":{"id":"doi:10.1002/cta.2648","doi":"https://doi.org/10.1002/cta.2648","is_oa":false,"landing_page_url":"https://doi.org/10.1002/cta.2648","pdf_url":null,"source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032547410","display_name":"Abhilash Tirupathi","orcid":"https://orcid.org/0000-0001-7555-425X","observed_orcids":["https://orcid.org/0000-0001-7555-425X"]},"institutions":[{"id":"https://openalex.org/I121750182","display_name":"National Institute of Technology Warangal","ror":"https://ror.org/017ebfz38","country_code":"IN","type":"education","lineage":["https://openalex.org/I121750182"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Abhilash Tirupathi","raw_affiliation_strings":["Department of Electrical Engineering, National Institute of Technology Warangal, Warangal, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Institute of Technology Warangal, Warangal, India","institution_ids":["https://openalex.org/I121750182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063317333","display_name":"A. Kirubakaran","orcid":"https://orcid.org/0000-0002-3800-1776","observed_orcids":["https://orcid.org/0000-0002-3800-1776"]},"institutions":[{"id":"https://openalex.org/I121750182","display_name":"National Institute of Technology Warangal","ror":"https://ror.org/017ebfz38","country_code":"IN","type":"education","lineage":["https://openalex.org/I121750182"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Kirubakaran Annamalai","raw_affiliation_strings":["Department of Electrical Engineering, National Institute of Technology Warangal, Warangal, India"],"raw_orcid":"https://orcid.org/0000-0002-3800-1776","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Institute of Technology Warangal, Warangal, India","institution_ids":["https://openalex.org/I121750182"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108742983","display_name":"Veeramraju Tirumala Somasekhar","orcid":"https://orcid.org/0000-0002-4985-2955","observed_orcids":["https://orcid.org/0000-0002-4985-2955"]},"institutions":[{"id":"https://openalex.org/I121750182","display_name":"National Institute of Technology Warangal","ror":"https://ror.org/017ebfz38","country_code":"IN","type":"education","lineage":["https://openalex.org/I121750182"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Somasekhar Veeramraju Tirumala","raw_affiliation_strings":["Department of Electrical Engineering, National Institute of Technology Warangal, Warangal, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Institute of Technology Warangal, Warangal, India","institution_ids":["https://openalex.org/I121750182"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5063317333"],"corresponding_institution_ids":["https://openalex.org/I121750182"],"apc_list":{"value":3500,"currency":"USD","value_usd":3500},"apc_paid":null,"fwci":0.9874,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.73098821,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"47","issue":"9","first_page":"1435","last_page":"1445"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10228","display_name":"Multilevel Inverters and Converters","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10228","display_name":"Multilevel Inverters and Converters","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11102","display_name":"HVDC Systems and Fault Protection","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10175","display_name":"Advanced DC-DC Converters","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cascaded-multilevel-inverter","display_name":"cascaded multilevel inverter","score":0.7540000081062317},{"id":"https://openalex.org/keywords/single-dc-source","display_name":"single DC source","score":0.9089999794960022},{"id":"https://openalex.org/keywords/dc-link-capacitor-voltage-balancing","display_name":"DC-link capacitor voltage balancing","score":0.8820000290870667},{"id":"https://openalex.org/keywords/sinusoidal-pulse-width-modulation","display_name":"sinusoidal pulse width modulation","score":0.8859999775886536}],"concepts":[{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.7077387571334839},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.6672897338867188},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.6411334276199341},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.6195741891860962},{"id":"https://openalex.org/C34146451","wikidata":"https://www.wikidata.org/wiki/Q5048094","display_name":"Cascade","level":2,"score":0.5897470712661743},{"id":"https://openalex.org/C92746544","wikidata":"https://www.wikidata.org/wiki/Q585184","display_name":"Pulse-width modulation","level":3,"score":0.5717943906784058},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5412404537200928},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5370902419090271},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.533099353313446},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49580129981040955},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.48374319076538086},{"id":"https://openalex.org/C123079801","wikidata":"https://www.wikidata.org/wiki/Q750240","display_name":"Modulation (music)","level":2,"score":0.44421181082725525},{"id":"https://openalex.org/C173871940","wikidata":"https://www.wikidata.org/wiki/Q471846","display_name":"Three-phase","level":3,"score":0.4262959361076355},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3340049684047699},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28797662258148193},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.13226881623268127},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.084066241979599},{"id":"https://openalex.org/C42360764","wikidata":"https://www.wikidata.org/wiki/Q83588","display_name":"Chemical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C24890656","wikidata":"https://www.wikidata.org/wiki/Q82811","display_name":"Acoustics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1002/cta.2648","doi":"https://doi.org/10.1002/cta.2648","is_oa":false,"landing_page_url":"https://doi.org/10.1002/cta.2648","pdf_url":null,"source":{"id":"https://openalex.org/S92132303","display_name":"International Journal of Circuit Theory and Applications","issn_l":"0098-9886","issn":["0098-9886","1097-007X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1","poland-70","russia-white-list-2"],"host_organization":"https://openalex.org/P4310320595","host_organization_name":"Wiley","host_organization_lineage":["https://openalex.org/P4310320595"],"host_organization_lineage_names":["Wiley"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Circuit Theory and Applications","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8485000133514404,"display_name":"Affordable and clean energy"},{"id":"https://metadata.un.org/sdg/9","score":0.651199996471405,"display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1979403799","https://openalex.org/W1982199082","https://openalex.org/W2030973541","https://openalex.org/W2036179439","https://openalex.org/W2069225832","https://openalex.org/W2107183246","https://openalex.org/W2143952868","https://openalex.org/W2156232631","https://openalex.org/W2163013270","https://openalex.org/W2167630521","https://openalex.org/W2171202998","https://openalex.org/W2176853600","https://openalex.org/W2257305627","https://openalex.org/W2506731073","https://openalex.org/W2520048381","https://openalex.org/W2543635132","https://openalex.org/W2566815404","https://openalex.org/W2584440306","https://openalex.org/W2754303526","https://openalex.org/W2791391503","https://openalex.org/W2792264774","https://openalex.org/W2805578741","https://openalex.org/W2809575699","https://openalex.org/W2891740964","https://openalex.org/W2898928888","https://openalex.org/W4233539232","https://openalex.org/W4248779028","https://openalex.org/W4252430294"],"related_works":["https://openalex.org/W4392653335","https://openalex.org/W4391930013","https://openalex.org/W3038008547","https://openalex.org/W2936853755","https://openalex.org/W2168670807","https://openalex.org/W7133565992","https://openalex.org/W2771500604","https://openalex.org/W4231431343","https://openalex.org/W4416403565","https://openalex.org/W2083327467"],"abstract_inverted_index":{"Summary":[0],"This":[1],"paper":[2],"presents":[3],"a":[4,12,29,36,44,67,90,148],"new":[5],"structure":[6],"of":[7,32,43,47,53,135,163],"three\u2010phase":[8],"five\u2010level":[9,72],"inverter":[10,73,131],"with":[11,28,71],"single":[13,91],"direct":[14],"current":[15],"(DC)":[16],"source":[17,93],"for":[18,76,147],"low\u2010":[19,77],"and":[20,39,56,78,94,144],"medium\u2010voltage":[21,79],"applications.":[22],"The":[23,84,133],"proposed":[24,75,85,137,165],"configuration":[25],"is":[26,69,87,114,139],"built":[27],"cascade":[30],"connection":[31],"two\u2010level":[33],"cells":[34],"in":[35,81,116,125,151],"nested":[37],"form":[38],"owns":[40],"the":[41,54,102,130,136,154,161,164],"advantages":[42],"reduced":[45],"number":[46],"passive":[48],"components,":[49],"total":[50],"blocking":[51],"voltage":[52],"switches,":[55],"isolated":[57],"DC":[58,92],"sources.":[59],"In":[60],"order":[61],"to":[62,100,128,159],"make":[63],"this":[64],"topology":[65,138],"attractive,":[66],"comparison":[68],"made":[70],"topologies":[74],"applications":[80],"recent":[82],"years.":[83],"circuit":[86,98],"powered":[88],"using":[89,121],"an":[95],"auxiliary":[96],"voltage\u2010balancing":[97],"(AVBC)":[99],"maintain":[101],"desired":[103],"DC\u2010link":[104],"capacitor":[105],"voltages.":[106],"A":[107],"sinusoidal":[108],"pulse":[109],"width":[110],"modulation":[111],"(SPWM)":[112],"scheme":[113],"implemented":[115],"field\u2010programmable":[117],"gate":[118],"array":[119],"(FPGA),":[120],"Xilinx":[122],"blocks":[123],"developed":[124],"MATLAB/SIMULINK":[126],"environment,":[127],"control":[129],"switches.":[132],"performance":[134],"verified":[140],"through":[141],"MATLAB":[142],"simulation":[143],"prototype":[145],"model":[146],"step":[149],"change":[150],"load.":[152],"Finally,":[153],"experimental":[155],"results":[156],"are":[157],"presented":[158],"validate":[160],"effectiveness":[162],"topology.":[166]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":6}],"updated_date":"2026-10-30T12:39:25.321706","created_date":"2019-05-29T00:00:00"}