{"id":"https://openalex.org/W2940948459","doi":"https://doi.org/10.31142/ijtsrd14146","title":"Low Power Mix Logic Design Using Line Decoder: A Review","display_name":"Low Power Mix Logic Design Using Line Decoder: A Review","publication_year":2018,"publication_date":"2018-06-30","ids":{"openalex":"https://openalex.org/W2940948459","doi":"https://doi.org/10.31142/ijtsrd14146","mag":"2940948459"},"language":"en","primary_location":{"id":"doi:10.31142/ijtsrd14146","doi":"https://doi.org/10.31142/ijtsrd14146","is_oa":true,"landing_page_url":"https://doi.org/10.31142/ijtsrd14146","pdf_url":"https://www.ijtsrd.com/papers/ijtsrd14146.pdf","source":{"id":"https://openalex.org/S2914917527","display_name":"International Journal of Trend in Scientific Research and Development","issn_l":"2456-6470","issn":["2456-6470"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4322696778","host_organization_name":"Rekha Patel","host_organization_lineage":["https://openalex.org/P4322696778"],"host_organization_lineage_names":["Rekha Patel"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Trend in Scientific Research and Development","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://www.ijtsrd.com/papers/ijtsrd14146.pdf","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002341217","display_name":"Ku. Priyanka M. Raut","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Ku. Priyanka M. Raut","raw_affiliation_strings":["Department of Electronics & Telecommunication, DRGIT&R, Amravati, Maharashtra, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics & Telecommunication, DRGIT&R, Amravati, Maharashtra, India","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113965881","display_name":"Rutuja Deshmukh","orcid":"https://orcid.org/0000-0001-6337-1149","observed_orcids":["https://orcid.org/0000-0001-6337-1149"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dr. R. M. Deshmukh","raw_affiliation_strings":["Professor & Head, Department of Electronics & Telecommunication, DRGIT&R, Amravati, Maharashtra, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Professor & Head, Department of Electronics & Telecommunication, DRGIT&R, Amravati, Maharashtra, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":1,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":"Volume-2","issue":"Issue-4","first_page":"976","last_page":"980"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.00019999999494757503,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/low-power-design","display_name":"low power design","score":0.7250000238418579},{"id":"https://openalex.org/keywords/transmission-gate-logic","display_name":"transmission gate logic","score":0.843999981880188},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7440000176429749},{"id":"https://openalex.org/keywords/power-dissipation","display_name":"power dissipation","score":0.7789999842643738},{"id":"https://openalex.org/keywords/transistor-count-reduction","display_name":"transistor count reduction","score":0.9480000138282776},{"id":"https://openalex.org/keywords/vlsi-circuits","display_name":"VLSI circuits","score":0.7990000247955322}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5368856191635132},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.4576318860054016},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.41719263792037964},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.37917184829711914},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.210728257894516},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.040018707513809204},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.31142/ijtsrd14146","doi":"https://doi.org/10.31142/ijtsrd14146","is_oa":true,"landing_page_url":"https://doi.org/10.31142/ijtsrd14146","pdf_url":"https://www.ijtsrd.com/papers/ijtsrd14146.pdf","source":{"id":"https://openalex.org/S2914917527","display_name":"International Journal of Trend in Scientific Research and Development","issn_l":"2456-6470","issn":["2456-6470"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4322696778","host_organization_name":"Rekha Patel","host_organization_lineage":["https://openalex.org/P4322696778"],"host_organization_lineage_names":["Rekha Patel"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Trend in Scientific Research and Development","raw_type":"journal-article"},{"id":"pmh:oai:zenodo.org:3582518","doi":null,"is_oa":true,"landing_page_url":"https://zenodo.org/record/3582518","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"International Journal of Trend in Scientific Research and Development 2(4) 976-980","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"doi:10.31142/ijtsrd14146","doi":"https://doi.org/10.31142/ijtsrd14146","is_oa":true,"landing_page_url":"https://doi.org/10.31142/ijtsrd14146","pdf_url":"https://www.ijtsrd.com/papers/ijtsrd14146.pdf","source":{"id":"https://openalex.org/S2914917527","display_name":"International Journal of Trend in Scientific Research and Development","issn_l":"2456-6470","issn":["2456-6470"],"is_oa":true,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4322696778","host_organization_name":"Rekha Patel","host_organization_lineage":["https://openalex.org/P4322696778"],"host_organization_lineage_names":["Rekha Patel"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Journal of Trend in Scientific Research and Development","raw_type":"journal-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W2940948459.pdf","grobid_xml":"https://content.openalex.org/works/W2940948459.grobid-xml"},"referenced_works_count":9,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W2135955108","https://openalex.org/W2141849037","https://openalex.org/W2182422398","https://openalex.org/W2187983366","https://openalex.org/W2208031660","https://openalex.org/W2341599104","https://openalex.org/W4236346444","https://openalex.org/W6631122486"],"related_works":["https://openalex.org/W3165854730","https://openalex.org/W3197371908","https://openalex.org/W4254001349","https://openalex.org/W3009608439","https://openalex.org/W2895902477","https://openalex.org/W3211154232","https://openalex.org/W3175895936","https://openalex.org/W4236504038","https://openalex.org/W2891477690","https://openalex.org/W2788481001"],"abstract_inverted_index":{"In":[0],"todays":[1],"world,":[2],"as":[3,171,173,213],"the":[4,10,13,25,68,152,156,162,182],"technology":[5],"is":[6,32,123,161,186,204,227],"developing":[7],"so":[8],"rapidly":[9],"designing":[11],"of":[12,35,101,132,164,166,176,190,222],"systems":[14,22],"are":[15,27,65,93,109,197],"becoming":[16],"more":[17,19],"and":[18,57,79,82,178,196,219],"compact.In":[20],"some":[21],"even":[23],"if":[24],"circuits":[26,226],"not":[28],"compact;":[29],"still":[30],"there":[31,185],"a":[33,41,71,83,99,124],"need":[34,189],"less":[36,194],"power":[37,80,158,169,179,195,202,224],"consumption.This":[38],"brief":[39],"introduces":[40],"mixed":[42,113],"logic":[43,114],"design":[44,203],"method":[45],"for":[46,67],"line":[47],"decoders,":[48],"combining":[49],"transmission":[50],"gate":[51],"logic,":[52,56],"pass":[53],"transistor":[54,77,135,177],"dual":[55],"static":[58],"complementary":[59],"metal":[60],"semiconductor":[61],"(CMOS).Two":[62],"novel":[63],"topologies":[64],"presented":[66],"2-4":[69,115],"decoder:":[70],"14":[72],"topology":[73,85],"aiming":[74,86],"on":[75,87,151],"minimizing":[76],"count":[78],"dissipation":[81],"15-transistor":[84],"high":[88,208],"power-delay":[89],"performance.Both":[90],"inverting":[91],"decoders":[92,108],"implemented":[94],"in":[95,155,199,207],"each":[96],"case,":[97],"yielding":[98],"total":[100],"four":[102,105],"new":[103,106],"designs.Additionally,":[104],"4-16":[107],"designed":[110],"by":[111],"using":[112],"predecoders":[116],"combined":[117],"with":[118],"standard":[119],"CMOS":[120],"postdecoder.Low":[121],"Power":[122],"well":[125,172],"establishe":[126],"discipline;":[127],"it":[128],"has":[129],"undergone":[130],"lot":[131],"developments":[133],"from":[134],"sizing,":[136],"process":[137],"shrinkage,":[138],"voltage":[139],"scaling,":[140],"clock":[141],"gating,":[142],"etc.,":[143],"to":[144,149,167],"adiabatic":[145],"logic.This":[146],"paper":[147,160],"aims":[148],"elaborate":[150],"recent":[153],"trends":[154],"low":[157,201,223],"design.This":[159],"review":[163],"use":[165],"reduce":[168,174],"consumption":[170],"number":[175],"dissipation.":[180],"INTRODUCTION:In":[181],"modern":[183],"age,":[184],"an":[187],"immense":[188],"applications":[191],"which":[192],"consume":[193],"small":[198],"area.The":[200],"major":[205],"issue":[206],"performance":[209],"digital":[210,215],"system,":[211],"such":[212],"microprocessors,":[214],"signal":[216],"processors":[217],"(DSPs)":[218],"other":[220],"applications.Designing":[221],"VLSI":[225]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2019-05-03T00:00:00"}