{"id":"https://openalex.org/W2921787622","doi":"https://doi.org/10.1134/s1063739718070028","title":"Solving the Problems of Routing Interconnects with a Resynthesis for Reconfigurable Systems on a Chip","display_name":"Solving the Problems of Routing Interconnects with a Resynthesis for Reconfigurable Systems on a Chip","publication_year":2018,"publication_date":"2018-11-01","ids":{"openalex":"https://openalex.org/W2921787622","doi":"https://doi.org/10.1134/s1063739718070028","mag":"2921787622"},"language":"en","primary_location":{"id":"doi:10.1134/s1063739718070028","doi":"https://doi.org/10.1134/s1063739718070028","is_oa":false,"landing_page_url":"https://doi.org/10.1134/s1063739718070028","pdf_url":null,"source":{"id":"https://openalex.org/S170838215","display_name":"Russian Microelectronics","issn_l":"1063-7397","issn":["1063-7397","1608-3415","3034-5480"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["norway-1","poland-40","russia-white-list-2"],"host_organization":"https://openalex.org/P4310320267","host_organization_name":"Pleiades Publishing","host_organization_lineage":["https://openalex.org/P4310320267","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Pleiades Publishing","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Russian Microelectronics","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053906683","display_name":"S. V. Gavrilov","orcid":"https://orcid.org/0000-0003-0566-4482","observed_orcids":["https://orcid.org/0000-0003-0566-4482"]},"institutions":[{"id":"https://openalex.org/I1313323035","display_name":"Russian Academy of Sciences","ror":"https://ror.org/05qrfxd25","country_code":"RU","type":"government","lineage":["https://openalex.org/I1313323035"]},{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":true,"raw_author_name":"S. V. Gavrilov","raw_affiliation_strings":["Institute of Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia","institution_ids":["https://openalex.org/I1313323035","https://openalex.org/I4210096404"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013950156","display_name":"Daniil A. Zheleznikov","orcid":"https://orcid.org/0000-0003-2477-1793","observed_orcids":["https://orcid.org/0000-0003-2477-1793"]},"institutions":[{"id":"https://openalex.org/I1313323035","display_name":"Russian Academy of Sciences","ror":"https://ror.org/05qrfxd25","country_code":"RU","type":"government","lineage":["https://openalex.org/I1313323035"]},{"id":"https://openalex.org/I204490831","display_name":"National Research University of Electronic Technology","ror":"https://ror.org/02hf6mx60","country_code":"RU","type":"education","lineage":["https://openalex.org/I204490831"]},{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"D. A. Zheleznikov","raw_affiliation_strings":["Institute of Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia","National Research University MIET, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia","institution_ids":["https://openalex.org/I1313323035","https://openalex.org/I4210096404"]},{"raw_affiliation_string":"National Research University MIET, Moscow, Russia","institution_ids":["https://openalex.org/I204490831"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082049065","display_name":"Vasilii M. Khvatov","orcid":"https://orcid.org/0000-0003-2285-4341","observed_orcids":["https://orcid.org/0000-0003-2285-4341"]},"institutions":[{"id":"https://openalex.org/I1313323035","display_name":"Russian Academy of Sciences","ror":"https://ror.org/05qrfxd25","country_code":"RU","type":"government","lineage":["https://openalex.org/I1313323035"]},{"id":"https://openalex.org/I204490831","display_name":"National Research University of Electronic Technology","ror":"https://ror.org/02hf6mx60","country_code":"RU","type":"education","lineage":["https://openalex.org/I204490831"]},{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"V. M. Khvatov","raw_affiliation_strings":["Institute of Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia","National Research University MIET, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia","institution_ids":["https://openalex.org/I1313323035","https://openalex.org/I4210096404"]},{"raw_affiliation_string":"National Research University MIET, Moscow, Russia","institution_ids":["https://openalex.org/I204490831"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5053906683"],"corresponding_institution_ids":["https://openalex.org/I1313323035","https://openalex.org/I4210096404"],"apc_list":null,"apc_paid":null,"fwci":0.6687,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.68184254,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":"47","issue":"7","first_page":"516","last_page":"521"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9359999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9359999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.040800001472234726,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.020800000056624413,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnect-routing","display_name":"interconnect routing","score":0.800000011920929},{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.7139999866485596},{"id":"https://openalex.org/keywords/a-algorithm","display_name":"A* algorithm","score":0.8870000243186951},{"id":"https://openalex.org/keywords/computer-aided-design","display_name":"computer-aided design","score":0.7720000147819519}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7958707809448242},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7489602565765381},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.663532018661499},{"id":"https://openalex.org/C173870130","wikidata":"https://www.wikidata.org/wiki/Q8548","display_name":"Dijkstra's algorithm","level":4,"score":0.6231155395507812},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5139488577842712},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4809662401676178},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.47064536809921265},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4545229971408844},{"id":"https://openalex.org/C22590252","wikidata":"https://www.wikidata.org/wiki/Q1058754","display_name":"Shortest path problem","level":3,"score":0.4537794888019562},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.44920387864112854},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4466448426246643},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4183167815208435},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3943658471107483},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.3313508629798889},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.27714312076568604},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.19791972637176514},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1302165687084198},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11588048934936523},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1134/s1063739718070028","doi":"https://doi.org/10.1134/s1063739718070028","is_oa":false,"landing_page_url":"https://doi.org/10.1134/s1063739718070028","pdf_url":null,"source":{"id":"https://openalex.org/S170838215","display_name":"Russian Microelectronics","issn_l":"1063-7397","issn":["1063-7397","1608-3415","3034-5480"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["norway-1","poland-40","russia-white-list-2"],"host_organization":"https://openalex.org/P4310320267","host_organization_name":"Pleiades Publishing","host_organization_lineage":["https://openalex.org/P4310320267","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Pleiades Publishing","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Russian Microelectronics","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.7207000255584717,"display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1641177182","https://openalex.org/W1757537413","https://openalex.org/W1969483458","https://openalex.org/W1977850862","https://openalex.org/W2098557772","https://openalex.org/W2169528473"],"related_works":["https://openalex.org/W2921906179","https://openalex.org/W2537790318","https://openalex.org/W2759943396","https://openalex.org/W36234522","https://openalex.org/W2792159077","https://openalex.org/W1801332854","https://openalex.org/W570923387","https://openalex.org/W6910918773","https://openalex.org/W39691862","https://openalex.org/W2113143036"],"abstract_inverted_index":{"Abstract":[0],"The":[1],"existing":[2,23],"means":[3,26],"of":[4,13,62,74,101,116,153,181,206,233,251,269,275,287],"design":[5,253],"automation":[6],"are":[7,46,226],"focused":[8],"mainly":[9],"on":[10,67,159,163,171,190],"the":[11,22,60,68,75,105,110,113,117,124,150,167,182,187,193,204,222,228,249,261,266,270,282],"technology":[12],"foreign":[14,93],"manufacturers,":[15],"which":[16,89],"makes":[17],"it":[18],"necessary":[19],"to":[20,32,38,59,123,126,137,166],"adapt":[21],"methods":[24,129],"and":[25,31,82,141,242,258,272,284],"for":[27,48,104,112,130,149,155,186,235,265,281],"designing":[28],"reconfigurable":[29,64,157],"systems-on-a-chip":[30],"develop":[33,127],"domestic":[34,69],"specialized":[35],"CAD":[36],"tools":[37],"solve":[39],"urgent":[40],"problems":[41,52],"in":[42,53,221,260],"this":[43,96],"field.":[44],"Methods":[45],"proposed":[47],"solving":[49],"interconnection":[50],"routing":[51,131,152,273,286],"conjunction":[54],"with":[55],"logical":[56,114],"resynthesis,":[57],"applied":[58],"architecture":[61],"a":[63,156,160,179,191,197,210,218,231],"system-on-a-chip":[65],"based":[66,162,170],"field-programmable":[70],"gate":[71],"array":[72],"(FPGA)":[73],"Almaz-14":[76,119,168],"family.":[77],"Developers":[78],"from":[79],"JSC":[80],"\u201cNIIME\u201d":[81],"PJSC":[83],"\u201cMicron\u201d":[84],"laid":[85],"broad":[86],"configurational":[87],"solutions,":[88],"do":[90],"not":[91],"have":[92,121],"analogues,":[94],"into":[95,139],"crystal.":[97],"A":[98],"wide":[99],"range":[100],"additional":[102,207],"elements":[103,234,274],"configuration,":[106,236],"as":[107,109,215,217,237,239,277,279],"well":[108,216,238,278],"potentialities":[111],"resynthesis":[115],"FPGA":[118],"chip,":[120],"led":[122],"need":[125],"new":[128],"interconnections":[132,154],"that":[133],"would":[134],"allow":[135],"us":[136],"take":[138],"account":[140],"use":[142,268],"these":[143],"architectural":[144],"features.":[145],"An":[146],"efficient":[147],"algorithm":[148,172,177,184],"automatic":[151],"system":[158],"chip":[161],"FPGAs":[164],"belonging":[165],"family":[169],"A*":[173],"is":[174],"developed.":[175],"This":[176,245],"represents":[178],"modification":[180],"classical":[183],"searching":[185],"shortest":[188],"path":[189],"graph,":[192],"Dijkstra":[194],"algorithm,":[195],"including":[196],"mixed":[198],"switching":[199,208],"graph":[200],"model.":[201],"To":[202],"describe":[203],"variety":[205],"elements,":[209],"special":[211,219],"generalized":[212],"mathematical":[213],"model,":[214],"interface":[220],"command":[223],"language":[224,264],"Tcl":[225],"developed,":[227],"latter":[229],"includes":[230],"list":[232],"their":[240],"description":[241],"functional":[243],"purpose.":[244],"work":[246],"has":[247],"increased":[248],"efficiency":[250],"computer-aided":[252],"using":[254],"programmed":[255],"mechanisms":[256,280],"developed":[257],"implemented":[259],"C":[262],"programming":[263],"optimal":[267],"configuration":[271],"FPGAs,":[276],"complete":[283],"entire":[285],"interconnections.":[288]},"counts_by_year":[{"year":2020,"cited_by_count":7}],"updated_date":"2026-10-01T08:54:57.152042","created_date":"2019-03-22T00:00:00"}
