{"id":"https://openalex.org/W2921106965","doi":"https://doi.org/10.1109/eiconrus.2019.8657285","title":"Development and Verification of Various Formats of Functional Blocks Libraries as a Part of the Design Flow for FPGAs","display_name":"Development and Verification of Various Formats of Functional Blocks Libraries as a Part of the Design Flow for FPGAs","publication_year":2019,"publication_date":"2019-01-01","ids":{"openalex":"https://openalex.org/W2921106965","doi":"https://doi.org/10.1109/eiconrus.2019.8657285","mag":"2921106965"},"language":"en","primary_location":{"id":"doi:10.1109/eiconrus.2019.8657285","doi":"https://doi.org/10.1109/eiconrus.2019.8657285","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eiconrus.2019.8657285","pdf_url":null,"source":{"id":"https://openalex.org/S4306422515","display_name":"IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026474373","display_name":"Tatiana V. Garbulina","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Tatiana V. Garbulina","raw_affiliation_strings":["Institute for Design Problems in Microelectronics RAS (IPPM RAS), Zelenograd, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Design Problems in Microelectronics RAS (IPPM RAS), Zelenograd, Moscow, Russia","institution_ids":["https://openalex.org/I4210096404"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082049065","display_name":"Vasilii M. Khvatov","orcid":"https://orcid.org/0000-0003-2285-4341","observed_orcids":["https://orcid.org/0000-0003-2285-4341"]},"institutions":[{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Vasiliy M. Khvatov","raw_affiliation_strings":["Institute for Design Problems in Microelectronics RAS (IPPM RAS), Zelenograd, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Design Problems in Microelectronics RAS (IPPM RAS), Zelenograd, Moscow, Russia","institution_ids":["https://openalex.org/I4210096404"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013950156","display_name":"Daniil A. Zheleznikov","orcid":"https://orcid.org/0000-0003-2477-1793","observed_orcids":["https://orcid.org/0000-0003-2477-1793"]},"institutions":[{"id":"https://openalex.org/I4210096404","display_name":"Institute for Design Problems in Microelectronics","ror":"https://ror.org/00t7t9a43","country_code":"RU","type":"facility","lineage":["https://openalex.org/I4210096404"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"Daniil A. Zheleznikov","raw_affiliation_strings":["Institute for Design Problems in Microelectronics RAS (IPPM RAS), Zelenograd, Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Design Problems in Microelectronics RAS (IPPM RAS), Zelenograd, Moscow, Russia","institution_ids":["https://openalex.org/I4210096404"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210096404"],"apc_list":null,"apc_paid":null,"fwci":1.5842,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.79337629,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1687","last_page":"1691"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6884999871253967,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.6884999871253967,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.28130000829696655,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.027000000700354576,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/fpga","display_name":"FPGA","score":0.699999988079071},{"id":"https://openalex.org/keywords/fpga-design-flow","display_name":"FPGA design flow","score":0.8730000257492065},{"id":"https://openalex.org/keywords/computer-aided-design","display_name":"computer-aided design","score":0.9070000052452087},{"id":"https://openalex.org/keywords/fpga-architecture","display_name":"FPGA architecture","score":0.5440000295639038},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"integrated circuit design","score":0.5649999976158142}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8269820213317871},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7527160048484802},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6653407216072083},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6118193864822388},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5389856100082397},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.5228469967842102},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.5199241042137146},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4927974045276642},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4899086356163025},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4814307391643524},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4607037603855133},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.4145689904689789},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.2306138575077057},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1736803948879242},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16620925068855286},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eiconrus.2019.8657285","doi":"https://doi.org/10.1109/eiconrus.2019.8657285","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eiconrus.2019.8657285","pdf_url":null,"source":{"id":"https://openalex.org/S4306422515","display_name":"IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.7207000255584717,"display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1641177182","https://openalex.org/W1669302834","https://openalex.org/W2160640369"],"related_works":["https://openalex.org/W2897732498","https://openalex.org/W4386664018","https://openalex.org/W2387024331","https://openalex.org/W7046373655","https://openalex.org/W3028955404","https://openalex.org/W3155313565","https://openalex.org/W1481053433","https://openalex.org/W4313886697","https://openalex.org/W2104155838","https://openalex.org/W2147317993"],"abstract_inverted_index":{"At":[0],"present,":[1],"within":[2],"the":[3,18,43,50,57,84,110,117,127],"framework":[4],"of":[5,42,59,61,68,86,104,119,129],"ensuring":[6],"technological":[7],"independence,":[8],"more":[9,11],"and":[10,31,45,66,114,122],"domestic":[12],"FPGAs":[13],"began":[14],"to":[15,96,108,115],"appear":[16],"on":[17,49,83],"Russian":[19],"market.":[20],"Each":[21],"FPGA":[22,51,99,133],"should":[23],"be":[24],"provided":[25],"with":[26],"a":[27],"computer-aided":[28],"design":[29,54,80,134],"system":[30],"its":[32],"own":[33,138],"software":[34,89],"environment.":[35],"An":[36,77],"important":[37],"aspect":[38],"for":[39],"increasing":[40],"speed":[41],"development":[44,65,121],"modeling":[46],"integrated":[47],"circuits":[48],"in":[52],"this":[53,105],"flow":[55,81,135],"is":[56,72,107],"presence":[58],"libraries":[60,71],"functional":[62,69],"blocks.":[63],"The":[64,102],"verification":[67],"elements":[70],"an":[73,130],"extensive":[74],"time-consuming":[75],"task.":[76],"architecturally":[78,131],"independent":[79,132],"based":[82],"experience":[85],"using":[87,136],"foreign":[88],"products":[90],"was":[91],"developed":[92],"by":[93],"IPPM":[94],"RAS":[95],"support":[97],"new":[98],"architecture":[100],"types.":[101],"purpose":[103],"work":[106],"review":[109],"library":[111],"formats":[112],"used":[113],"describe":[116],"process":[118],"their":[120],"verification.":[123],"We":[124],"also":[125],"show":[126],"steps":[128],"our":[137],"CAD":[139],"system.":[140]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2}],"updated_date":"2026-10-05T09:50:58.205359","created_date":"2019-03-22T00:00:00"}
