{"id":"https://openalex.org/W2917618495","doi":"https://doi.org/10.1049/iet-cds.2018.5259","title":"Symbiotic organisms search algorithm for optimal design of CMOS two\u2010stage op\u2010amp with nulling resistor and robust bias circuit","display_name":"Symbiotic organisms search algorithm for optimal design of CMOS two\u2010stage op\u2010amp with nulling resistor and robust bias circuit","publication_year":2019,"publication_date":"2019-02-25","ids":{"openalex":"https://openalex.org/W2917618495","doi":"https://doi.org/10.1049/iet-cds.2018.5259","mag":"2917618495"},"language":"en","primary_location":{"id":"doi:10.1049/iet-cds.2018.5259","doi":"https://doi.org/10.1049/iet-cds.2018.5259","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cds.2018.5259","pdf_url":null,"source":{"id":"https://openalex.org/S4210208150","display_name":"IET Circuits Devices & Systems","issn_l":"1751-858X","issn":["1751-858X","1751-8598"],"is_oa":false,"is_in_doaj":true,"is_core":true,"listed_in":["cwts-core","doaj","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Circuits, Devices & Systems","raw_type":"journal-article"},"volume":null,"type":"article","indexed_in":["crossref","doaj"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076849928","display_name":"Sumalya Ghosh","orcid":"https://orcid.org/0000-0002-4115-1222","observed_orcids":["https://orcid.org/0000-0002-4115-1222"]},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Sumalya Ghosh","raw_affiliation_strings":["Department of Electronics and Communication Engineering National Institute of Technology Durgapur India","Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering National Institute of Technology Durgapur India","institution_ids":["https://openalex.org/I155837530"]},{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India","institution_ids":["https://openalex.org/I155837530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087343297","display_name":"Bishnu Prasad De","orcid":"https://orcid.org/0000-0002-1146-1692","observed_orcids":["https://orcid.org/0000-0002-1146-1692"]},"institutions":[{"id":"https://openalex.org/I67357951","display_name":"KIIT University","ror":"https://ror.org/00k8zt527","country_code":"IN","type":"education","lineage":["https://openalex.org/I67357951"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bishnu Prasad De","raw_affiliation_strings":["School of Electronics Engineering Kalinga Institute of Industrial Technology Bhubaneswar India","School of Electronics Engineering, Kalinga Institute of Industrial Technology, Bhubaneswar, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering Kalinga Institute of Industrial Technology Bhubaneswar India","institution_ids":["https://openalex.org/I67357951"]},{"raw_affiliation_string":"School of Electronics Engineering, Kalinga Institute of Industrial Technology, Bhubaneswar, India","institution_ids":["https://openalex.org/I67357951"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012097209","display_name":"Rajib Kar","orcid":"https://orcid.org/0000-0002-5789-0580","observed_orcids":["https://orcid.org/0000-0002-5789-0580"]},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rajib Kar","raw_affiliation_strings":["Department of Electronics and Communication Engineering National Institute of Technology Durgapur India","Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering National Institute of Technology Durgapur India","institution_ids":["https://openalex.org/I155837530"]},{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India","institution_ids":["https://openalex.org/I155837530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112556114","display_name":"Ashis Kumar Mal","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I155837530","display_name":"National Institute of Technology Durgapur","ror":"https://ror.org/04ds0jm32","country_code":"IN","type":"education","lineage":["https://openalex.org/I155837530"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ashis Kumar Mal","raw_affiliation_strings":["Department of Electronics and Communication Engineering National Institute of Technology Durgapur India","Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering National Institute of Technology Durgapur India","institution_ids":["https://openalex.org/I155837530"]},{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India","institution_ids":["https://openalex.org/I155837530"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5076849928"],"corresponding_institution_ids":["https://openalex.org/I155837530"],"apc_list":{"value":2540,"currency":"USD","value_usd":2540},"apc_paid":null,"fwci":0.8311,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.67238244,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"13","issue":"5","first_page":"679","last_page":"688"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.7318999767303467,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.7318999767303467,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10100","display_name":"Metaheuristic Optimization Algorithms Research","score":0.18930000066757202,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.02370000071823597,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/symbiotic-organisms-search-algorithm","display_name":"symbiotic organisms search algorithm","score":0.9819999933242798},{"id":"https://openalex.org/keywords/transistor-sizing","display_name":"transistor sizing","score":0.6480000019073486},{"id":"https://openalex.org/keywords/circuit-area-minimization","display_name":"circuit area minimization","score":0.7590000033378601},{"id":"https://openalex.org/keywords/power-dissipation","display_name":"power dissipation","score":0.9110000133514404},{"id":"https://openalex.org/keywords/evolutionary-optimization","display_name":"evolutionary optimization","score":0.6589999794960022}],"concepts":[{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.8020504713058472},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7934781312942505},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.6968801617622375},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6154583096504211},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6063702702522278},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5236710906028748},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.502103328704834},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4916298985481262},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.43408477306365967},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3018921911716461},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2739018201828003},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2307555079460144}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1049/iet-cds.2018.5259","doi":"https://doi.org/10.1049/iet-cds.2018.5259","is_oa":false,"landing_page_url":"https://doi.org/10.1049/iet-cds.2018.5259","pdf_url":null,"source":{"id":"https://openalex.org/S4210208150","display_name":"IET Circuits Devices & Systems","issn_l":"1751-858X","issn":["1751-858X","1751-8598"],"is_oa":false,"is_in_doaj":true,"is_core":true,"listed_in":["cwts-core","doaj","jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310311714","host_organization_name":"Institution of Engineering and Technology","host_organization_lineage":["https://openalex.org/P4310311714"],"host_organization_lineage_names":["Institution of Engineering and Technology"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IET Circuits, Devices & Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"sustainable_development_goals_aurora":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1185709174","https://openalex.org/W1492264771","https://openalex.org/W1536945048","https://openalex.org/W1597620877","https://openalex.org/W1857053585","https://openalex.org/W1925428099","https://openalex.org/W1964239621","https://openalex.org/W2015115262","https://openalex.org/W2065183815","https://openalex.org/W2076702864","https://openalex.org/W2085737665","https://openalex.org/W2088542116","https://openalex.org/W2090455930","https://openalex.org/W2091638274","https://openalex.org/W2106476087","https://openalex.org/W2112308092","https://openalex.org/W2119581540","https://openalex.org/W2141989178","https://openalex.org/W2152195021","https://openalex.org/W2166282246","https://openalex.org/W2277520548","https://openalex.org/W2296309070","https://openalex.org/W2417076733","https://openalex.org/W2493943902","https://openalex.org/W2567184137","https://openalex.org/W2766952848","https://openalex.org/W2767168476","https://openalex.org/W2782909759","https://openalex.org/W2793178100","https://openalex.org/W2793262983","https://openalex.org/W2808554454"],"related_works":["https://openalex.org/W1976724132","https://openalex.org/W3210903312","https://openalex.org/W3195565859","https://openalex.org/W2168638127","https://openalex.org/W2018547716","https://openalex.org/W2145001846","https://openalex.org/W2170642797","https://openalex.org/W962052505","https://openalex.org/W2941936807","https://openalex.org/W1967188269"],"abstract_inverted_index":{"This":[0],"study":[1],"suggests":[2],"an":[3],"evolutionary":[4],"technique":[5],"namely":[6],"symbiotic":[7],"organisms":[8],"search":[9],"(SOS)":[10],"algorithm":[11,60,76,106],"based":[12,30,72,100],"optimal":[13],"designs":[14],"of":[15,47,53],"two":[16],"different":[17],"analogue":[18],"very\u2010large\u2010scale":[19],"integration":[20],"circuits.":[21,97,129],"The":[22,44],"configurations":[23],"considered":[24],"here":[25],"are":[26,77,91],"nulling":[27],"resistor":[28],"compensation":[29],"complementary":[31],"metal\u2013oxide\u2013semiconductor":[32,54],"(CMOS)":[33],"two\u2010stage":[34,37],"op\u2010amp":[35,39,128],"and":[36,122],"CMOS":[38],"with":[40,79],"robust":[41],"bias":[42],"circuit.":[43,69],"prime":[45],"goal":[46],"this":[48],"work":[49],"is":[50],"the":[51,58,63,67,74,88,96,104,113,118,126],"sizing":[52],"(MOS)":[55],"transistors":[56],"employing":[57],"SOS":[59,75,105],"to":[61,112],"optimise":[62],"area":[64,121],"occupied":[65],"by":[66],"individual":[68],"Design":[70],"results":[71,84,101,110],"on":[73],"authenticated":[78],"SPICE":[80,82,99],"simulation.":[81],"simulation":[83],"reveal":[85],"that":[86,103],"all":[87],"design":[89],"specifications":[90],"firmly":[92],"satisfied":[93],"for":[94,125],"both":[95],"Moreover,":[98],"show":[102],"provides":[107],"much":[108],"better":[109],"compared":[111],"earlier":[114],"reported":[115],"techniques":[116],"regarding":[117],"gain,":[119],"MOS":[120],"power":[123],"dissipation":[124],"abovementioned":[127]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-08-27T14:10:00.468798","created_date":"2025-10-10T00:00:00"}