{"id":"https://openalex.org/W2904883963","doi":"https://doi.org/10.23919/iwlpc.2018.8573261","title":"Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic Rf Mems/Cmos","display_name":"Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic Rf Mems/Cmos","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2904883963","doi":"https://doi.org/10.23919/iwlpc.2018.8573261","mag":"2904883963"},"language":"en","primary_location":{"id":"doi:10.23919/iwlpc.2018.8573261","doi":"https://doi.org/10.23919/iwlpc.2018.8573261","is_oa":false,"landing_page_url":"https://doi.org/10.23919/iwlpc.2018.8573261","pdf_url":null,"source":{"id":"https://openalex.org/S7407088356","display_name":"International Wafer Level Packaging Conference (IWLPC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Wafer Level Packaging Conference (IWLPC)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113797641","display_name":"Rameen Hadizadeh","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rameen Hadizadeh","raw_affiliation_strings":["WiSpry, Inc., Irvine, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"WiSpry, Inc., Irvine, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087813179","display_name":"Anssi Laitinen","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Anssi Laitinen","raw_affiliation_strings":["WiSpry, Inc., Irvine, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"WiSpry, Inc., Irvine, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028550107","display_name":"David Molinero","orcid":"https://orcid.org/0000-0002-4419-4957","observed_orcids":["https://orcid.org/0000-0002-4419-4957"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"David Molinero","raw_affiliation_strings":["WiSpry, Inc., Irvine, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"WiSpry, Inc., Irvine, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"Nelson Pereira","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405254070","display_name":"Amkor Technology (Portugal)","ror":"https://ror.org/01cgw9e63","country_code":"PT","type":"company","lineage":["https://openalex.org/I4405254070","https://openalex.org/I68887363"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Nelson Pereira","raw_affiliation_strings":["Amkor Technology, Inc., Porto, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Amkor Technology, Inc., Porto, Portugal","institution_ids":["https://openalex.org/I4405254070"]}]},{"author_position":"last","author":{"id":null,"display_name":"Marcio Pinheiro","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I4405254070","display_name":"Amkor Technology (Portugal)","ror":"https://ror.org/01cgw9e63","country_code":"PT","type":"company","lineage":["https://openalex.org/I4405254070","https://openalex.org/I68887363"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Marcio Pinheiro","raw_affiliation_strings":["Amkor Technology, Inc., Porto, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Amkor Technology, Inc., Porto, Portugal","institution_ids":["https://openalex.org/I4405254070"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.9981,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.84238266,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9535999894142151,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9535999894142151,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10369","display_name":"Advanced MEMS and NEMS Technologies","score":0.023000000044703484,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10460","display_name":"Electronic Packaging and Soldering Technologies","score":0.01360000018030405,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rf-mems","display_name":"RF MEMS","score":0.8109999895095825},{"id":"https://openalex.org/keywords/cmos-mems-integration","display_name":"CMOS-MEMS integration","score":0.8169999718666077},{"id":"https://openalex.org/keywords/redistribution-layer","display_name":"redistribution layer","score":0.9340000152587891},{"id":"https://openalex.org/keywords/solder-interconnects","display_name":"solder interconnects","score":0.6890000104904175},{"id":"https://openalex.org/keywords/mechanical-shock","display_name":"mechanical shock","score":0.5149999856948853},{"id":"https://openalex.org/keywords/self-resonant-frequency","display_name":"self-resonant frequency","score":0.8130000233650208},{"id":"https://openalex.org/keywords/parasitic-losses","display_name":"parasitic losses","score":0.8420000076293945},{"id":"https://openalex.org/keywords/0-18-mum-cmos","display_name":"0.18 \u03bcm CMOS","score":0.7379999756813049}],"concepts":[{"id":"https://openalex.org/C94709252","wikidata":"https://www.wikidata.org/wiki/Q570628","display_name":"Ball grid array","level":3,"score":0.7360056638717651},{"id":"https://openalex.org/C2780288131","wikidata":"https://www.wikidata.org/wiki/Q4017648","display_name":"Wafer-level packaging","level":3,"score":0.7087896466255188},{"id":"https://openalex.org/C2778080309","wikidata":"https://www.wikidata.org/wiki/Q99454494","display_name":"Small form factor","level":2,"score":0.6350880861282349},{"id":"https://openalex.org/C79072407","wikidata":"https://www.wikidata.org/wiki/Q432439","display_name":"Flip chip","level":4,"score":0.6313035488128662},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5827693343162537},{"id":"https://openalex.org/C126233035","wikidata":"https://www.wikidata.org/wiki/Q5101572","display_name":"Chip-scale package","level":3,"score":0.5627106428146362},{"id":"https://openalex.org/C186260285","wikidata":"https://www.wikidata.org/wiki/Q759494","display_name":"Integrated circuit packaging","level":3,"score":0.5597302913665771},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.5458829402923584},{"id":"https://openalex.org/C62064638","wikidata":"https://www.wikidata.org/wiki/Q553878","display_name":"Design for manufacturability","level":2,"score":0.5393893718719482},{"id":"https://openalex.org/C37977207","wikidata":"https://www.wikidata.org/wiki/Q175561","display_name":"Microelectromechanical systems","level":2,"score":0.5228334069252014},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49569499492645264},{"id":"https://openalex.org/C68812741","wikidata":"https://www.wikidata.org/wiki/Q636609","display_name":"Fan-out","level":3,"score":0.48419836163520813},{"id":"https://openalex.org/C193149544","wikidata":"https://www.wikidata.org/wiki/Q7122904","display_name":"Packaging engineering","level":2,"score":0.4823126792907715},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4755932092666626},{"id":"https://openalex.org/C2778638305","wikidata":"https://www.wikidata.org/wiki/Q7406100","display_name":"Wafer-scale integration","level":3,"score":0.47222140431404114},{"id":"https://openalex.org/C146667757","wikidata":"https://www.wikidata.org/wiki/Q1457198","display_name":"System in package","level":3,"score":0.4709787368774414},{"id":"https://openalex.org/C69567186","wikidata":"https://www.wikidata.org/wiki/Q5358403","display_name":"Electronic packaging","level":2,"score":0.4667136073112488},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4630430340766907},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.45788776874542236},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.4525725543498993},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3837033212184906},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3377673327922821},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3298962414264679},{"id":"https://openalex.org/C50296614","wikidata":"https://www.wikidata.org/wiki/Q211387","display_name":"Soldering","level":2,"score":0.27882081270217896},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.21199646592140198},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.13402393460273743},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12181761860847473},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.12052115797996521},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.08168104290962219},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C68928338","wikidata":"https://www.wikidata.org/wiki/Q131790","display_name":"Adhesive","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.23919/iwlpc.2018.8573261","doi":"https://doi.org/10.23919/iwlpc.2018.8573261","is_oa":false,"landing_page_url":"https://doi.org/10.23919/iwlpc.2018.8573261","pdf_url":null,"source":{"id":"https://openalex.org/S7407088356","display_name":"International Wafer Level Packaging Conference (IWLPC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 International Wafer Level Packaging Conference (IWLPC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2884188421","https://openalex.org/W2912074405"],"related_works":["https://openalex.org/W2072078440","https://openalex.org/W4402834426","https://openalex.org/W3010569551","https://openalex.org/W2096157399","https://openalex.org/W3147568422","https://openalex.org/W4309811420","https://openalex.org/W2028317843","https://openalex.org/W2058459217","https://openalex.org/W3089098386","https://openalex.org/W3027401491"],"abstract_inverted_index":{"Navigating":[0],"the":[1,20,61,106,137,140,191,210,228,276],"trade-offs":[2],"between":[3,209],"performance,":[4],"size,":[5],"cost":[6],"and":[7,19,154,166,185,239],"reliability":[8,261],"can":[9,54],"be":[10],"a":[11,43,70,95,118,163,186,204,220,286],"challenge":[12,222],"when":[13],"considering":[14],"integrated":[15,127,225],"circuit":[16,273],"(IC)":[17],"packaging":[18,48,82,88,116,161,174,234],"end-application.":[21],"The":[22],"integration":[23],"of":[24,36,46,65,86,108,139,177,188,207,223,265,279,288],"micro-electromechanical":[25],"systems":[26],"(MEMS),":[27],"either":[28],"monolithic":[29],"or":[30,156],"heterogeneous,":[31],"introduces":[32],"yet":[33],"another":[34],"level":[35,96],"complexity":[37],"that":[38],"has":[39,90],"only":[40],"recently":[41],"been":[42],"major":[44],"focus":[45],"multi-device":[47],"[1].":[49],"Wafer-level":[50],"fan-out":[51],"(WLFO)":[52],"technology":[53],"enable":[55],"improvements":[56],"in":[57,63,73,197,217],"several":[58],"areas,":[59],"primarily":[60],"reduction":[62],"size":[64,196],"parasitic":[66,290],"interconnects":[67],"and,":[68],"proportionally,":[69],"drastic":[71],"decrease":[72],"overall":[74,289],"form-factor":[75,208],"as":[76,285],"compared":[77],"to":[78,94,142,182,190,230,250,259],"more":[79],"ubiquitous":[80],"chip-scale":[81],"solutions.":[83],"Widespread":[84],"adoption":[85],"WLFO":[87,109,173],"[2]":[89],"driven":[91],"implementation":[92],"costs":[93],"competitive":[97],"with":[98,128,145],"traditional":[99],"fan-in":[100],"wafer-level":[101],"packaging.":[102],"This":[103],"study":[104],"quantifies":[105],"benefits":[107],"versus":[110],"flip-chip":[111],"land":[112],"grid":[113,193],"array":[114,126],"(FCLGA)":[115],"for":[117],"radio":[119],"frequency":[120,283],"(RF)":[121],"MEMS":[122],"digital":[123],"tunable":[124],"capacitor":[125],"180nm":[129],"CMOS":[130],"technology.":[131],"RF":[132,263],"performance":[133],"hinges":[134],"critically":[135],"upon":[136],"ability":[138,229],"package":[141,212],"transfer":[143],"signals":[144],"minimal":[146],"impedance,":[147],"necessitating":[148],"shortened":[149],"redistribution":[150],"layer":[151],"(RDL)":[152],"paths":[153],"reduced,":[155],"removed,":[157],"solder":[158,169],"interconnects.":[159],"Flip-chip":[160],"requires":[162],"multi-layered":[164],"substrate":[165],"an":[167],"intermediate":[168],"interconnect":[170],"while":[171],"chip-first":[172],"makes":[175],"use":[176],"direct":[178,205],"Cu":[179],"RDL":[180],"bond":[181],"die":[183],"pads":[184],"single-level":[187],"routing":[189],"ball":[192],"array.":[194],"Die":[195],"both":[198],"cases":[199],"is":[200,215,227],"1.8x2.2x0.3mm,":[201],"which":[202],"enables":[203],"comparison":[206],"two":[211],"types.":[213],"Manufacturability":[214],"addressed":[216],"this":[218],"study;":[219],"primary":[221,277],"monolithically":[224],"MEMS/CMOS":[226],"survive":[231],"typical":[232],"IC":[233],"processes":[235],"wherein":[236],"thermal,":[237],"mechanical":[238,252],"electrical":[240],"overstress":[241],"may":[242],"occur.":[243],"Daisy":[244],"chain":[245],"packaged":[246,255,267],"parts":[247,256,268],"were":[248,257],"subjected":[249,258],"board-level":[251],"shock.":[253],"Functional":[254],"component-level":[260],"stresses.":[262],"characterization":[264],"functional":[266],"was":[269],"conducted":[270],"on":[271],"printed":[272],"boards":[274],"(PCB);":[275],"figure":[278],"merit":[280],"being":[281],"self-resonance":[282],"(SRF)":[284],"result":[287],"losses.":[291]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2}],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2018-12-22T00:00:00"}
