{"id":"https://openalex.org/W2903833844","doi":"https://doi.org/10.1109/norchip.2018.8573523","title":"Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment","display_name":"Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment","publication_year":2018,"publication_date":"2018-10-01","ids":{"openalex":"https://openalex.org/W2903833844","doi":"https://doi.org/10.1109/norchip.2018.8573523","mag":"2903833844"},"language":"en","primary_location":{"id":"doi:10.1109/norchip.2018.8573523","doi":"https://doi.org/10.1109/norchip.2018.8573523","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2018.8573523","pdf_url":null,"source":{"id":"https://openalex.org/S7407087125","display_name":"IEEE Nordic Circuits and Systems Conference (NorCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005644571","display_name":"Ruei-Ting Chien","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ruei-Ting Chien","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058593712","display_name":"Yi-Lun Liao","orcid":"https://orcid.org/0000-0002-5299-6749","observed_orcids":["https://orcid.org/0000-0002-5299-6749"]},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Lun Liao","raw_affiliation_strings":["Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Chien-An Wang","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-An Wang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035019211","display_name":"Yu-Cheng Li","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Cheng Li","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040956103","display_name":"Yi-Chang Lu","orcid":"https://orcid.org/0000-0002-7638-0367","observed_orcids":["https://orcid.org/0000-0002-7638-0367"]},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yi-Chang Lu","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.36399999260902405,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.36399999260902405,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10015","display_name":"Genomics and Phylogenetic Studies","score":0.19519999623298645,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.13850000500679016,"subfield":{"id":"https://openalex.org/subfields/2614","display_name":"Theoretical Computer Science"},"field":{"id":"https://openalex.org/fields/26","display_name":"Mathematics"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiple-sequence-alignment","display_name":"multiple sequence alignment","score":0.9629999995231628},{"id":"https://openalex.org/keywords/hardware-accelerators","display_name":"hardware accelerators","score":0.9629999995231628},{"id":"https://openalex.org/keywords/parallel-processing-elements","display_name":"parallel processing elements","score":0.8479999899864197},{"id":"https://openalex.org/keywords/fpga-implementation","display_name":"FPGA implementation","score":0.871999979019165},{"id":"https://openalex.org/keywords/asic-implementation","display_name":"ASIC implementation","score":0.9549999833106995},{"id":"https://openalex.org/keywords/speedup","display_name":"speedup","score":0.4860000014305115}],"concepts":[{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8393824100494385},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7886019349098206},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.756912350654602},{"id":"https://openalex.org/C2776190703","wikidata":"https://www.wikidata.org/wiki/Q488148","display_name":"Slicing","level":2,"score":0.7140457630157471},{"id":"https://openalex.org/C37404715","wikidata":"https://www.wikidata.org/wiki/Q380679","display_name":"Dynamic programming","level":2,"score":0.6719302535057068},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6655673980712891},{"id":"https://openalex.org/C2778112365","wikidata":"https://www.wikidata.org/wiki/Q3511065","display_name":"Sequence (biology)","level":2,"score":0.6069913506507874},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.6030057668685913},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5935177206993103},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.5766935348510742},{"id":"https://openalex.org/C88031987","wikidata":"https://www.wikidata.org/wiki/Q1377767","display_name":"Multiple sequence alignment","level":5,"score":0.48175573348999023},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4542378783226013},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45368918776512146},{"id":"https://openalex.org/C45484198","wikidata":"https://www.wikidata.org/wiki/Q827246","display_name":"Sequence alignment","level":4,"score":0.3686456084251404},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33249878883361816},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3229581117630005},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24764272570610046},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14362266659736633},{"id":"https://openalex.org/C167625842","wikidata":"https://www.wikidata.org/wiki/Q899763","display_name":"Peptide sequence","level":3,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/norchip.2018.8573523","doi":"https://doi.org/10.1109/norchip.2018.8573523","is_oa":false,"landing_page_url":"https://doi.org/10.1109/norchip.2018.8573523","pdf_url":null,"source":{"id":"https://openalex.org/S7407087125","display_name":"IEEE Nordic Circuits and Systems Conference (NorCAS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1992519395","https://openalex.org/W2001006312","https://openalex.org/W2056251063","https://openalex.org/W2063639943","https://openalex.org/W2068448872","https://openalex.org/W2074231493","https://openalex.org/W2102502076","https://openalex.org/W2106882534","https://openalex.org/W2125703639","https://openalex.org/W2127774996","https://openalex.org/W2139582206","https://openalex.org/W2144362290","https://openalex.org/W2285549169","https://openalex.org/W2613312483"],"related_works":["https://openalex.org/W1995754226","https://openalex.org/W1559959829","https://openalex.org/W2001954549","https://openalex.org/W2053908469","https://openalex.org/W2154782736","https://openalex.org/W2991998747","https://openalex.org/W1972517864","https://openalex.org/W3045270239","https://openalex.org/W4245861326","https://openalex.org/W4386710083"],"abstract_inverted_index":{"Three":[0],"sequence":[1,12,31],"alignment":[2,13,44],"can":[3,40,92],"be":[4],"used":[5],"to":[6,69],"improve":[7],"the":[8,42,99],"accuracy":[9],"of":[10,29,72],"multiple":[11],"in":[14,46,67],"genomics.":[15],"In":[16,55],"this":[17],"paper,":[18],"we":[19,57],"design":[20,39],"a":[21,47,59],"hardware":[22,76],"accelerator":[23,77],"for":[24,63],"three-dimensional":[25,64],"dynamic":[26,65],"programming":[27,66],"algorithm":[28],"three":[30],"alignment.":[32],"By":[33],"utilizing":[34],"parallel":[35],"processing":[36],"elements,":[37],"our":[38],"find":[41],"optimal":[43],"scores":[45],"shorter":[48],"time":[49],"than":[50],"that":[51],"required":[52],"by":[53],"software.":[54],"addition,":[56],"propose":[58],"memory-efficient":[60],"slicing":[61],"method":[62],"order":[68],"process":[70],"sequences":[71],"longer":[73],"lengths.":[74],"The":[75,85],"is":[78],"implemented":[79],"on":[80],"both":[81],"FPGA":[82],"and":[83],"ASIC.":[84],"ASIC":[86],"implementation":[87],"using":[88],"TSMC":[89],"40nm":[90],"technology":[91],"achieve":[93],"at":[94],"least":[95],"160\u00d7":[96],"speedup":[97],"over":[98],"software":[100],"implementation.":[101]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2018-12-22T00:00:00"}
