{"id":"https://openalex.org/W2901375374","doi":"https://doi.org/10.1109/intercon.2018.8526442","title":"A Novel Architecture for Implementation of Quasi Delay Insensitive Finite State Machines","display_name":"A Novel Architecture for Implementation of Quasi Delay Insensitive Finite State Machines","publication_year":2018,"publication_date":"2018-08-01","ids":{"openalex":"https://openalex.org/W2901375374","doi":"https://doi.org/10.1109/intercon.2018.8526442","mag":"2901375374"},"language":"en","primary_location":{"id":"doi:10.1109/intercon.2018.8526442","doi":"https://doi.org/10.1109/intercon.2018.8526442","is_oa":false,"landing_page_url":"https://doi.org/10.1109/intercon.2018.8526442","pdf_url":null,"source":{"id":"https://openalex.org/S4306498332","display_name":"IEEE International Conference on Electronics, Electrical Engineering and Computing (INTERCON)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE XXV International Conference on Electronics, Electrical Engineering and Computing (INTERCON)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009078527","display_name":"Duarte L. Oliveira","orcid":"https://orcid.org/0000-0002-9704-6616","observed_orcids":["https://orcid.org/0000-0002-9704-6616"]},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Duarte L. Oliveira","raw_affiliation_strings":["Electronic Engineering Division, Instituto Tecnol\u00f3gico de Aeron\u00e1utica \u2013 ITA, SP, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronic Engineering Division, Instituto Tecnol\u00f3gico de Aeron\u00e1utica \u2013 ITA, SP, Brazil","institution_ids":["https://openalex.org/I107428990"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036872409","display_name":"Orlando Verducci Junior","orcid":"https://orcid.org/0000-0002-8620-8149","observed_orcids":["https://orcid.org/0000-0002-8620-8149"]},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Orlando Verducci","raw_affiliation_strings":["Electronic Engineering Division, Instituto Tecnol\u00f3gico de Aeron\u00e1utica \u2013 ITA, SP, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronic Engineering Division, Instituto Tecnol\u00f3gico de Aeron\u00e1utica \u2013 ITA, SP, Brazil","institution_ids":["https://openalex.org/I107428990"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032301784","display_name":"Vitor L. V. Torres","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Vitor L. V. Torres","raw_affiliation_strings":["Electronic Engineering Division, Instituto Tecnol\u00f3gico de Aeron\u00e1utica \u2013 ITA, SP, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronic Engineering Division, Instituto Tecnol\u00f3gico de Aeron\u00e1utica \u2013 ITA, SP, Brazil","institution_ids":["https://openalex.org/I107428990"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074539605","display_name":"Osamu Saotome","orcid":"https://orcid.org/0000-0002-1568-9299","observed_orcids":["https://orcid.org/0000-0002-1568-9299"]},"institutions":[{"id":"https://openalex.org/I107428990","display_name":"Instituto Tecnol\u00f3gico de Aeron\u00e1utica","ror":"https://ror.org/05vh67662","country_code":"BR","type":"education","lineage":["https://openalex.org/I107428990"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Osamu Saotome","raw_affiliation_strings":["Electronic Engineering Division, Instituto Tecnol\u00f3gico de Aeron\u00e1utica \u2013 ITA, SP, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronic Engineering Division, Instituto Tecnol\u00f3gico de Aeron\u00e1utica \u2013 ITA, SP, Brazil","institution_ids":["https://openalex.org/I107428990"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085951867","display_name":"Robson Luiz Moreno","orcid":"https://orcid.org/0000-0002-1938-7685","observed_orcids":["https://orcid.org/0000-0002-1938-7685"]},"institutions":[{"id":"https://openalex.org/I8165072","display_name":"Universidade Federal de Itajub\u00e1","ror":"https://ror.org/00235nr42","country_code":"BR","type":"education","lineage":["https://openalex.org/I8165072"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Robson L. Moreno","raw_affiliation_strings":["Universidade Federal de Itajub\u00e1, IESTI, Minas Gerais, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal de Itajub\u00e1, IESTI, Minas Gerais, Brazil","institution_ids":["https://openalex.org/I8165072"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028885987","display_name":"Joao B. Brandolin","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I107371206","display_name":"Federal Institute of S\u00e3o Paulo","ror":"https://ror.org/005pn5z34","country_code":"BR","type":"education","lineage":["https://openalex.org/I107371206"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Joao B. Brandolin","raw_affiliation_strings":["Electrical Department, Federal Institute of Education, Science and Technology of S\u00e3o Paulo, S\u00e3o Paulo, SP, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Department, Federal Institute of Education, Science and Technology of S\u00e3o Paulo, S\u00e3o Paulo, SP, Brazil","institution_ids":["https://openalex.org/I107371206"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3996,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.41559293,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":"18","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.002099999925121665,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.0006000000284984708,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/quasi-delay-insensitive-circuits","display_name":"quasi-delay-insensitive circuits","score":0.9570000171661377},{"id":"https://openalex.org/keywords/asynchronous-finite-state-machines","display_name":"asynchronous finite state machines","score":0.9729999899864197},{"id":"https://openalex.org/keywords/dual-rail-logic","display_name":"dual-rail logic","score":0.7940000295639038},{"id":"https://openalex.org/keywords/ultra-low-power-design","display_name":"ultra-low power design","score":0.8109999895095825},{"id":"https://openalex.org/keywords/dynamic-power-reduction","display_name":"dynamic power reduction","score":0.824999988079071},{"id":"https://openalex.org/keywords/static-power-reduction","display_name":"static power reduction","score":0.9399999976158142},{"id":"https://openalex.org/keywords/latency-reduction","display_name":"latency reduction","score":0.7059999704360962}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8062937259674072},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.731532871723175},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.667600691318512},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5551201105117798},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5450906157493591},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5240887999534607},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.44110584259033203},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.43550363183021545},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4272994101047516},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.41154155135154724},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3955440819263458},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38611382246017456},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3503972887992859},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20984280109405518},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13012391328811646},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12555846571922302},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10728281736373901},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09044823050498962},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/intercon.2018.8526442","doi":"https://doi.org/10.1109/intercon.2018.8526442","is_oa":false,"landing_page_url":"https://doi.org/10.1109/intercon.2018.8526442","pdf_url":null,"source":{"id":"https://openalex.org/S4306498332","display_name":"IEEE International Conference on Electronics, Electrical Engineering and Computing (INTERCON)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE XXV International Conference on Electronics, Electrical Engineering and Computing (INTERCON)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1992723344","https://openalex.org/W1997274586","https://openalex.org/W2010534954","https://openalex.org/W2012845553","https://openalex.org/W2051380786","https://openalex.org/W2058948603","https://openalex.org/W2088643059","https://openalex.org/W2121914493","https://openalex.org/W2126251049","https://openalex.org/W2133040205","https://openalex.org/W2137978379","https://openalex.org/W2143436053","https://openalex.org/W2150872535","https://openalex.org/W2171480615","https://openalex.org/W2289615949","https://openalex.org/W2805706505","https://openalex.org/W2810031419","https://openalex.org/W4253227026","https://openalex.org/W6679664800"],"related_works":["https://openalex.org/W2921435813","https://openalex.org/W3199886896","https://openalex.org/W2805706505","https://openalex.org/W3094380447","https://openalex.org/W1988589788","https://openalex.org/W2126251049","https://openalex.org/W3175078384","https://openalex.org/W4294675083","https://openalex.org/W2978753127","https://openalex.org/W3157683208"],"abstract_inverted_index":{"Due":[0],"to":[1,36,48,53,58],"the":[2,8,29,96,125,129,164],"increasing":[3],"demand":[4],"for":[5,10,86,133],"mobile":[6],"devices,":[7],"search":[9],"ultra-low-power":[11],"projects":[12],"is":[13,28,122],"becoming":[14],"a":[15,21,83],"priority.":[16],"One":[17],"technique":[18],"that":[19],"allows":[20],"strong":[22],"reduction":[23,138],"of":[24,139,150,163],"circuits":[25,45,60],"dissipated":[26],"power":[27,153],"sub-threshold":[30,118],"voltage":[31],"operation,":[32],"but":[33],"it":[34],"leads":[35],"some":[37],"drawbacks.":[38],"The":[39,108,120],"QDI":[40,87,161],"(Quasi":[41],"Delay":[42],"Insensitive)":[43],"asynchronous":[44,78],"class":[46],"shows":[47],"be":[49],"an":[50,77,136],"interesting":[51],"solution":[52],"these":[54],"problems,":[55],"when":[56,157],"compared":[57,158],"synchronous":[59],"and":[61,102,128,141,144,154],"in":[62,76,90,95,117],"CMOS-UDSM":[63],"(Ultra":[64],"Deep":[65],"Sub-Micron)":[66],"technology.":[67],"Asynchronous":[68],"finite":[69],"state":[70],"machines":[71],"(AFSMs)":[72],"are":[73,111],"important":[74],"components":[75],"system.":[79],"This":[80],"paper":[81],"proposes":[82],"new":[84],"architecture":[85,121],"AFSMs":[88],"described":[89],"Extended":[91],"Burst-Mode":[92],"specification,":[93],"implemented":[94],"dual-rail":[97],"style":[98],"using":[99],"basic":[100],"gates":[101],"memory":[103],"based":[104],"on":[105],"RS":[106],"latches.":[107],"resulting":[109],"XBM_AFSMs":[110],"QDI,":[112],"so":[113],"they":[114],"can":[115],"operate":[116],"voltage.":[119],"presented":[123],"through":[124],"case":[126],"study":[127],"obtained":[130],"QDI_XBM_AFSM":[131],"presents":[132],"three":[134],"benchmarks":[135],"average":[137],"24.4%,":[140],"48.3%,":[142],"49.6%":[143],"49.2%":[145],"respectively,":[146],"latency":[147],"time,":[148],"number":[149],"LUTs,":[151],"dynamic":[152],"static":[155],"power,":[156],"with":[159],"four":[160],"controllers":[162],"literature.":[165]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2018-11-29T00:00:00"}
