{"id":"https://openalex.org/W2891035882","doi":"https://doi.org/10.1016/j.ifacol.2018.07.141","title":"Automatic Software-Based Self Test Generation for Embedded Processors","display_name":"Automatic Software-Based Self Test Generation for Embedded Processors","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2891035882","doi":"https://doi.org/10.1016/j.ifacol.2018.07.141","mag":"2891035882"},"language":"en","primary_location":{"id":"doi:10.1016/j.ifacol.2018.07.141","doi":"https://doi.org/10.1016/j.ifacol.2018.07.141","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.ifacol.2018.07.141","pdf_url":null,"source":{"id":"https://openalex.org/S2898405271","display_name":"IFAC-PapersOnLine","issn_l":"2405-8963","issn":["2405-8963","2405-8971"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1","poland-20","vabb-shw"],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFAC-PapersOnLine","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"diamond","oa_url":"https://doi.org/10.1016/j.ifacol.2018.07.141","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058439825","display_name":"J\u00e1n Hudec","orcid":"https://orcid.org/0000-0002-9291-5704","observed_orcids":["https://orcid.org/0000-0002-9291-5704"]},"institutions":[{"id":"https://openalex.org/I110757952","display_name":"Slovak University of Technology in Bratislava","ror":"https://ror.org/0561ghm58","country_code":"SK","type":"education","lineage":["https://openalex.org/I110757952"]}],"countries":["SK"],"is_corresponding":true,"raw_author_name":"J\u00e1n Hudec","raw_affiliation_strings":["Institute of Computer Engineering and Applied Informatics Faculty of Informatics and Information Technologies Slovak University of Technology 84216 Bratislava, Slovakia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Computer Engineering and Applied Informatics Faculty of Informatics and Information Technologies Slovak University of Technology 84216 Bratislava, Slovakia","institution_ids":["https://openalex.org/I110757952"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5058439825"],"corresponding_institution_ids":["https://openalex.org/I110757952"],"apc_list":{"value":0,"currency":"USD","value_usd":0},"apc_paid":null,"fwci":0.3611,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.68670432,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":"51","issue":"6","first_page":"125","last_page":"130"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.8657000064849854,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.8657000064849854,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.12049999833106995,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.0071000000461936,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/software-based-self-test","display_name":"software-based self-test","score":0.7950000166893005},{"id":"https://openalex.org/keywords/test-case-generation","display_name":"test case generation","score":0.7369999885559082},{"id":"https://openalex.org/keywords/embedded-processors","display_name":"embedded processors","score":0.9729999899864197},{"id":"https://openalex.org/keywords/functional-testing","display_name":"functional testing","score":0.8479999899864197},{"id":"https://openalex.org/keywords/genetic-algorithm","display_name":"genetic algorithm","score":0.9929999709129333},{"id":"https://openalex.org/keywords/evolution-strategies","display_name":"evolution strategies","score":0.9919999837875366},{"id":"https://openalex.org/keywords/code-coverage","display_name":"code coverage","score":0.9769999980926514},{"id":"https://openalex.org/keywords/risc-processor","display_name":"RISC processor","score":0.777999997138977},{"id":"https://openalex.org/keywords/processor-verification","display_name":"processor verification","score":0.5889999866485596}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8137392997741699},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.5788441300392151},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5040456652641296},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.45111986994743347},{"id":"https://openalex.org/C53942775","wikidata":"https://www.wikidata.org/wiki/Q1211721","display_name":"Code coverage","level":3,"score":0.4490816295146942},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4360443353652954},{"id":"https://openalex.org/C80823478","wikidata":"https://www.wikidata.org/wiki/Q4493432","display_name":"Functional testing","level":3,"score":0.43514472246170044},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.41795480251312256},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.41065287590026855},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33794933557510376},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.3061799108982086},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.18045955896377563},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1690346598625183},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/j.ifacol.2018.07.141","doi":"https://doi.org/10.1016/j.ifacol.2018.07.141","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.ifacol.2018.07.141","pdf_url":null,"source":{"id":"https://openalex.org/S2898405271","display_name":"IFAC-PapersOnLine","issn_l":"2405-8963","issn":["2405-8963","2405-8971"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1","poland-20","vabb-shw"],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFAC-PapersOnLine","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1016/j.ifacol.2018.07.141","doi":"https://doi.org/10.1016/j.ifacol.2018.07.141","is_oa":true,"landing_page_url":"https://doi.org/10.1016/j.ifacol.2018.07.141","pdf_url":null,"source":{"id":"https://openalex.org/S2898405271","display_name":"IFAC-PapersOnLine","issn_l":"2405-8963","issn":["2405-8963","2405-8971"],"is_oa":true,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","jufo-1","norway-1","poland-20","vabb-shw"],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFAC-PapersOnLine","raw_type":"journal-article"},"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320335322","display_name":"European Regional Development Fund","ror":"https://ror.org/00k4n6c32"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W37542656","https://openalex.org/W39775609","https://openalex.org/W1499264356","https://openalex.org/W1763200058","https://openalex.org/W1995827686","https://openalex.org/W2010508810","https://openalex.org/W2061104937","https://openalex.org/W2100488671","https://openalex.org/W2107332201","https://openalex.org/W2108446983","https://openalex.org/W2133952354","https://openalex.org/W2143605660","https://openalex.org/W2155112542","https://openalex.org/W2155341425","https://openalex.org/W2162696040","https://openalex.org/W2561238474","https://openalex.org/W4232940466","https://openalex.org/W4243513274"],"related_works":["https://openalex.org/W2999211172","https://openalex.org/W1667822267","https://openalex.org/W2561238474","https://openalex.org/W2119050364","https://openalex.org/W2155112542","https://openalex.org/W2742988238","https://openalex.org/W2105522986","https://openalex.org/W2115386046","https://openalex.org/W2463298697","https://openalex.org/W2126042558"],"abstract_inverted_index":{"The":[0,108],"paper":[1],"deals":[2],"with":[3,103],"automatic":[4],"software-based":[5,75],"test":[6,90],"generation":[7,91],"for":[8,70],"processors.":[9],"Processors":[10,23],"are":[11,40,57],"basic":[12],"blocks":[13],"of":[14,38,73,83,98,127,141],"current":[15],"complex":[16],"systems":[17],"on":[18,95,115],"chip":[19],"and":[20,64,100,125],"embedded":[21],"systems.":[22],"testing":[24,47],"can":[25],"be":[26],"extended":[27],"by":[28,80],"functional":[29,89],"tests":[30,39,44,50,55,76],"or":[31,48],"using":[32,104,117],"various":[33,105],"application":[34],"programs.":[35],"Such":[36],"types":[37,140],"serving":[41],"as":[42,49],"additional":[43],"to":[45,110],"structural":[46],"used":[51],"in":[52,133],"verification.":[53],"Functional":[54],"(programs)":[56],"generated":[58],"over":[59,138],"an":[60],"instruction":[61],"set":[62],"architecture":[63],"processor":[65,85],"model":[66,97],"description.":[67],"A":[68,87],"metric":[69],"quality":[71],"evaluation":[72],"the":[74,111,118,128,134],"is":[77,93],"obviously":[78],"provided":[79],"code":[81],"coverage":[82],"a":[84],"model.":[86],"new":[88],"method":[92],"based":[94,114],"VHDL":[96],"processors":[99],"genetic":[101],"algorithms":[102],"evolutionary":[106],"strategies.":[107],"contribution":[109],"SBST":[112],"methods":[113,130],"GAs":[116],"latest":[119],"defined":[120],"ES":[121],"was":[122],"identified.":[123],"Functionality":[124],"effectiveness":[126],"developed":[129],"were":[131],"evaluated":[132],"implemented":[135],"system":[136],"AGenMIX":[137],"two":[139],"RISC":[142],"processor.":[143]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-11-10T11:39:43.021295","created_date":"2018-09-27T00:00:00"}