{"id":"https://openalex.org/W2801898480","doi":"https://doi.org/10.1109/lssc.2018.2827880","title":"A 0.009 mm2 Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS","display_name":"A 0.009 mm2 Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS","publication_year":2018,"publication_date":"2018-03-01","ids":{"openalex":"https://openalex.org/W2801898480","doi":"https://doi.org/10.1109/lssc.2018.2827880","mag":"2801898480"},"language":"en","primary_location":{"id":"doi:10.1109/lssc.2018.2827880","doi":"https://doi.org/10.1109/lssc.2018.2827880","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lssc.2018.2827880","pdf_url":null,"source":{"id":"https://openalex.org/S4210192596","display_name":"IEEE Solid-State Circuits Letters","issn_l":"2573-9603","issn":["2573-9603"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-b","jufo-1","norway-1","poland-20","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Solid-State Circuits Letters","raw_type":"journal-article"},"volume":null,"type":"article","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044546029","display_name":"David M. Moore","orcid":"https://orcid.org/0000-0002-2848-7733","observed_orcids":["https://orcid.org/0000-0002-2848-7733"]},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David M. Moore","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":"https://orcid.org/0000-0002-2848-7733","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019737131","display_name":"Thucydides Xanthopoulos","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Thucydides Xanthopoulos","raw_affiliation_strings":["Cavium Inc., Marlborough, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cavium Inc., Marlborough, MA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039303017","display_name":"Scott Meninger","orcid":"https://orcid.org/0000-0001-8680-9502","observed_orcids":["https://orcid.org/0000-0001-8680-9502"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Scott Meninger","raw_affiliation_strings":["Cavium Inc., Marlborough, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cavium Inc., Marlborough, MA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052125657","display_name":"David D. Wentzloff","orcid":"https://orcid.org/0000-0002-9308-8392","observed_orcids":["https://orcid.org/0000-0002-9308-8392"]},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David D. Wentzloff","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA"],"raw_orcid":"https://orcid.org/0000-0002-9308-8392","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2645,"currency":"USD","value_usd":2645},"apc_paid":null,"fwci":0.9553,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.7314166,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":87,"max":98},"biblio":{"volume":"1","issue":"3","first_page":"74","last_page":"77"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/all-digital-phase-locked-loop","display_name":"all-digital phase-locked loop","score":0.9789999723434448},{"id":"https://openalex.org/keywords/clock-generation","display_name":"clock generation","score":0.6959999799728394},{"id":"https://openalex.org/keywords/clock-distribution","display_name":"clock distribution","score":0.9829999804496765},{"id":"https://openalex.org/keywords/many-core-processors","display_name":"many-core processors","score":0.8450000286102295},{"id":"https://openalex.org/keywords/phase-interpolator","display_name":"phase interpolator","score":0.8100000023841858},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"time-to-digital converter","score":0.9139999747276306},{"id":"https://openalex.org/keywords/standard-cell-library","display_name":"standard cell library","score":0.6539999842643738},{"id":"https://openalex.org/keywords/period-jitter","display_name":"period jitter","score":0.7170000076293945},{"id":"https://openalex.org/keywords/14nm-finfet","display_name":"14nm FinFET","score":0.859000027179718},{"id":"https://openalex.org/keywords/wide-tuning-range","display_name":"wide tuning range","score":0.460999995470047}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.7282788157463074},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.6912727355957031},{"id":"https://openalex.org/C167872736","wikidata":"https://www.wikidata.org/wiki/Q5276224","display_name":"Digitally controlled oscillator","level":5,"score":0.674704909324646},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6540268659591675},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6439688801765442},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5330250263214111},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5029227137565613},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.436400830745697},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.43094539642333984},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.42478641867637634},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4053972363471985},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35778266191482544},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3489423394203186},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3081333041191101},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23182526230812073},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.215094655752182},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1989876627922058},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.17599263787269592},{"id":"https://openalex.org/C26907483","wikidata":"https://www.wikidata.org/wiki/Q5253479","display_name":"Delay line oscillator","level":4,"score":0.1176941990852356},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/lssc.2018.2827880","doi":"https://doi.org/10.1109/lssc.2018.2827880","is_oa":false,"landing_page_url":"https://doi.org/10.1109/lssc.2018.2827880","pdf_url":null,"source":{"id":"https://openalex.org/S4210192596","display_name":"IEEE Solid-State Circuits Letters","issn_l":"2573-9603","issn":["2573-9603"],"is_oa":false,"is_in_doaj":false,"is_core":true,"listed_in":["cwts-core","dongbi-b","jufo-1","norway-1","poland-20","russia-white-list-2"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Solid-State Circuits Letters","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.428600013256073}],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1576786792","https://openalex.org/W1967823490","https://openalex.org/W2006427734","https://openalex.org/W2019720625","https://openalex.org/W2108458508","https://openalex.org/W2147533202","https://openalex.org/W2275003682","https://openalex.org/W2526148665","https://openalex.org/W2593145514","https://openalex.org/W2594147613"],"related_works":["https://openalex.org/W4402474264","https://openalex.org/W2147533202","https://openalex.org/W1989484081","https://openalex.org/W2965968461","https://openalex.org/W4412972295","https://openalex.org/W4308089895","https://openalex.org/W2147460185","https://openalex.org/W2569198588","https://openalex.org/W2041998100","https://openalex.org/W2115356790"],"abstract_inverted_index":{"An":[0],"automatically":[1],"placed-and-routed":[2],"all-digital":[3],"PLL":[4],"for":[5],"high-performance":[6],"clock":[7,79],"generation":[8],"and":[9,24,61,64,89],"distribution":[10],"in":[11,84],"many-core":[12],"processors":[13],"is":[14,35,48,70,114],"presented.":[15],"The":[16,44,78,96],"proposed":[17],"design":[18,76,97],"leverages":[19],"a":[20,41,85,99,117],"phase":[21,42],"domain":[22],"architecture,":[23],"features":[25,98],"an":[26,91],"embedded":[27],"TDC":[28,33],"constructed":[29],"from":[30,102],"standard":[31,45],"cells.":[32],"resolution":[34],"enhanced":[36],"through":[37],"the":[38,74],"use":[39],"of":[40,66,93,111,120],"interpolator.":[43],"cell":[46],"library":[47],"extended":[49],"with":[50,116],"custom":[51],"oscillator":[52],"cells":[53],"are":[54],"designed":[55],"to":[56,104],"achieve":[57],"optimized":[58],"power,":[59],"performance,":[60],"area.":[62],"Timing":[63],"handling":[65],"potentially":[67],"metastable":[68],"paths":[69],"additionally":[71],"handled":[72],"by":[73],"digital":[75],"How.":[77],"generator":[80],"has":[81],"been":[82],"fabricated":[83],"14-nm":[86],"FinFET":[87],"process,":[88],"occupies":[90],"area":[92],"0.009":[94],"mm2.":[95],"tuning":[100],"range":[101],"1.0":[103],"5.5":[105],"GHz":[106],"(80%).":[107],"Output":[108],"period":[109],"jitter":[110],"1.29":[112],"ps":[113],"achieved":[115],"power":[118],"consumption":[119],"9.7":[121],"mW.":[122]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":4}],"updated_date":"2026-11-04T10:54:05.112534","created_date":"2018-05-17T00:00:00"}