{"id":"https://openalex.org/W2770372249","doi":"https://doi.org/10.1109/iccd.2017.119","title":"A Design-for-Test Solution for Monolithic 3D Integrated Circuits","display_name":"A Design-for-Test Solution for Monolithic 3D Integrated Circuits","publication_year":2017,"publication_date":"2017-11-01","ids":{"openalex":"https://openalex.org/W2770372249","doi":"https://doi.org/10.1109/iccd.2017.119","mag":"2770372249"},"language":"en","primary_location":{"id":"doi:10.1109/iccd.2017.119","doi":"https://doi.org/10.1109/iccd.2017.119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2017.119","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049240930","display_name":"Abhishek Koneru","orcid":"https://orcid.org/0000-0002-3808-7303","observed_orcids":["https://orcid.org/0000-0002-3808-7303"]},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Abhishek Koneru","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Duke University, Durham, NC"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Duke University, Durham, NC","institution_ids":["https://openalex.org/I170897317"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016961561","display_name":"Sukeshwar Kannan","orcid":"https://orcid.org/0000-0003-4107-2126","observed_orcids":["https://orcid.org/0000-0003-4107-2126"]},"institutions":[{"id":"https://openalex.org/I35662394","display_name":"GlobalFoundries (United States)","ror":"https://ror.org/02h0ps145","country_code":"US","type":"company","lineage":["https://openalex.org/I35662394"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sukeshwar Kannan","raw_affiliation_strings":["GLOBALFOUNDRIES US Inc, Malta, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"GLOBALFOUNDRIES US Inc, Malta, NY","institution_ids":["https://openalex.org/I35662394"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033880864","display_name":"Krishnendu Chakrabarty","orcid":"https://orcid.org/0000-0003-4475-6435","observed_orcids":["https://orcid.org/0000-0003-4475-6435"]},"institutions":[{"id":"https://openalex.org/I170897317","display_name":"Duke University","ror":"https://ror.org/00py81415","country_code":"US","type":"education","lineage":["https://openalex.org/I170897317"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krishnendu Chakrabarty","raw_affiliation_strings":["Duke University, Durham, NC, US"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Duke University, Durham, NC, US","institution_ids":["https://openalex.org/I170897317"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.356,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.81151524,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":93,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"685","last_page":"688"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.003800000064074993,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/monolithic-3d-integration","display_name":"monolithic 3D integration","score":0.8960000276565552},{"id":"https://openalex.org/keywords/design-for-testability","display_name":"design for testability","score":0.8740000128746033},{"id":"https://openalex.org/keywords/defect-density","display_name":"defect density","score":0.718999981880188},{"id":"https://openalex.org/keywords/yield","display_name":"yield","score":0.48100000619888306},{"id":"https://openalex.org/keywords/through-silicon-vias","display_name":"through-silicon vias","score":0.8199999928474426}],"concepts":[{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.6374827027320862},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.619322657585144},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49482792615890503},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4563103914260864},{"id":"https://openalex.org/C544956773","wikidata":"https://www.wikidata.org/wiki/Q670","display_name":"Silicon","level":2,"score":0.45537739992141724},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43915629386901855},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.43513837456703186},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.43357133865356445},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43188273906707764},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.42364874482154846},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27122586965560913},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.20084238052368164},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.1968165636062622},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.19476580619812012},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.17938098311424255},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccd.2017.119","doi":"https://doi.org/10.1109/iccd.2017.119","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccd.2017.119","pdf_url":null,"source":{"id":"https://openalex.org/S4210174938","display_name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)","issn_l":"1063-6404","issn":["1063-6404","2576-6996"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE International Conference on Computer Design (ICCD)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5378999710083008,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1560950418","https://openalex.org/W1993815004","https://openalex.org/W2013397418","https://openalex.org/W2128998437","https://openalex.org/W2132155220","https://openalex.org/W2140069842","https://openalex.org/W2157629140","https://openalex.org/W2337205046","https://openalex.org/W2494513800","https://openalex.org/W2581008992","https://openalex.org/W2735555835","https://openalex.org/W2775005974"],"related_works":["https://openalex.org/W2885203734","https://openalex.org/W3184611608","https://openalex.org/W4285377714","https://openalex.org/W2946024207","https://openalex.org/W3020765505","https://openalex.org/W3214428847","https://openalex.org/W2887659151","https://openalex.org/W2808354633","https://openalex.org/W2807174038","https://openalex.org/W2775005974"],"abstract_inverted_index":{"Monolithic":[0],"three-dimensional":[1],"(M3D)":[2],"integration":[3,16],"has":[4],"the":[5,43,47,64,72,79],"potential":[6,59],"to":[7,14],"achieve":[8],"significantly":[9],"higher":[10],"device":[11],"density":[12],"compared":[13],"3D":[15],"based":[17,30,62],"on":[18,31,63],"through-silicon":[19],"vias":[20],"(TSVs).":[21],"We":[22,41],"propose":[23],"a":[24,58,83],"test":[25,33],"solution":[26,51,61,74,81],"for":[27,57,82],"M3D":[28],"ICs":[29],"dedicated":[32],"layers":[34],"that":[35,56,71],"are":[36],"inserted":[37],"between":[38],"functional":[39],"layers.":[40],"evaluate":[42],"cost":[44],"associated":[45],"with":[46,55],"proposed":[48,73],"design-for-test":[49],"(DfT)":[50],"and":[52,93],"compare":[53],"it":[54],"DfT":[60],"IEEE":[65],"Std.":[66],"P1838.":[67],"Our":[68],"results":[69],"show":[70],"is":[75],"more":[76],"cost-efficient":[77],"than":[78],"P1838-based":[80],"wide":[84],"range":[85],"of":[86],"inter-layer":[87],"via":[88],"(ILV)":[89],"density,":[90],"ILV":[91],"yield,":[92],"defect":[94],"density.":[95]},"counts_by_year":[{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":3}],"updated_date":"2026-11-07T11:25:07.637180","created_date":"2017-12-04T00:00:00"}
