{"id":"https://openalex.org/W2610686386","doi":"https://doi.org/10.1109/eiconrus.2017.7910575","title":"A technique of ASIC peak current estimation based on the resolution method","display_name":"A technique of ASIC peak current estimation based on the resolution method","publication_year":2017,"publication_date":"2017-01-01","ids":{"openalex":"https://openalex.org/W2610686386","doi":"https://doi.org/10.1109/eiconrus.2017.7910575","mag":"2610686386"},"language":"en","primary_location":{"id":"doi:10.1109/eiconrus.2017.7910575","doi":"https://doi.org/10.1109/eiconrus.2017.7910575","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eiconrus.2017.7910575","pdf_url":null,"source":{"id":"https://openalex.org/S4306422515","display_name":"IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026474373","display_name":"Tatiana V. Garbulina","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I204490831","display_name":"National Research University of Electronic Technology","ror":"https://ror.org/02hf6mx60","country_code":"RU","type":"education","lineage":["https://openalex.org/I204490831"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"T. V. Garbulina","raw_affiliation_strings":["Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia","institution_ids":["https://openalex.org/I204490831"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053906683","display_name":"S. V. Gavrilov","orcid":"https://orcid.org/0000-0003-0566-4482","observed_orcids":["https://orcid.org/0000-0003-0566-4482"]},"institutions":[{"id":"https://openalex.org/I204490831","display_name":"National Research University of Electronic Technology","ror":"https://ror.org/02hf6mx60","country_code":"RU","type":"education","lineage":["https://openalex.org/I204490831"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"S. V. Gavrilov","raw_affiliation_strings":["Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia","institution_ids":["https://openalex.org/I204490831"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005208391","display_name":"\u041a\u043e\u0440\u0448\u0443\u043d\u043e\u0432 \u0410\u043d\u0434\u0440\u0435\u0439 \u0412\u043b\u0430\u0434\u0438\u043c\u0438\u0440\u043e\u0432\u0438\u0447","orcid":"https://orcid.org/0000-0002-2470-5836","observed_orcids":["https://orcid.org/0000-0002-2470-5836"]},"institutions":[{"id":"https://openalex.org/I204490831","display_name":"National Research University of Electronic Technology","ror":"https://ror.org/02hf6mx60","country_code":"RU","type":"education","lineage":["https://openalex.org/I204490831"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"A. V. Korshunov","raw_affiliation_strings":["Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia","institution_ids":["https://openalex.org/I204490831"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103800336","display_name":"Daria I. Ryzhova","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I204490831","display_name":"National Research University of Electronic Technology","ror":"https://ror.org/02hf6mx60","country_code":"RU","type":"education","lineage":["https://openalex.org/I204490831"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"D. I. Ryzhova","raw_affiliation_strings":["Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia","institution_ids":["https://openalex.org/I204490831"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030879388","display_name":"\u0412\u043e\u043b\u043e\u0431\u0443\u0435\u0432 \u041f\u0430\u0432\u0435\u043b \u0421\u0435\u0440\u0433\u0435\u0435\u0432\u0438\u0447","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I204490831","display_name":"National Research University of Electronic Technology","ror":"https://ror.org/02hf6mx60","country_code":"RU","type":"education","lineage":["https://openalex.org/I204490831"]}],"countries":["RU"],"is_corresponding":false,"raw_author_name":"P. S. Volobuev","raw_affiliation_strings":["Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Microelectronic Circuits Design, National Research University of Electronic Technology, Zelenograd Moscow, Russia","institution_ids":["https://openalex.org/I204490831"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I204490831"],"apc_list":null,"apc_paid":null,"fwci":1.1643,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.70980456,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":"98","issue":null,"first_page":"394","last_page":"397"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.8628000020980835,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.8628000020980835,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.13109999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.001500000013038516,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/peak-current-estimation","display_name":"peak current estimation","score":0.9829999804496765},{"id":"https://openalex.org/keywords/asic","display_name":"ASIC","score":0.6140000224113464},{"id":"https://openalex.org/keywords/resolution-method","display_name":"resolution method","score":0.8930000066757202},{"id":"https://openalex.org/keywords/hypergraphs","display_name":"hypergraphs","score":0.7039999961853027},{"id":"https://openalex.org/keywords/branch-and-bound","display_name":"branch and bound","score":0.9079999923706055},{"id":"https://openalex.org/keywords/simultaneous-switching","display_name":"simultaneous switching","score":0.7319999933242798},{"id":"https://openalex.org/keywords/ir-drop","display_name":"IR drop","score":0.703000009059906},{"id":"https://openalex.org/keywords/cmos-circuits","display_name":"CMOS circuits","score":0.49000000953674316},{"id":"https://openalex.org/keywords/crosstalk","display_name":"crosstalk","score":0.6349999904632568},{"id":"https://openalex.org/keywords/substrate-noise","display_name":"substrate noise","score":0.753000020980835}],"concepts":[{"id":"https://openalex.org/C2781221856","wikidata":"https://www.wikidata.org/wiki/Q840247","display_name":"Hypergraph","level":2,"score":0.7106586694717407},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6637134552001953},{"id":"https://openalex.org/C77553402","wikidata":"https://www.wikidata.org/wiki/Q13222579","display_name":"Upper and lower bounds","level":2,"score":0.637000322341919},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6044944524765015},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.48358839750289917},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44700056314468384},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.44451531767845154},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.44241347908973694},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.42876917123794556},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4272735118865967},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3768976926803589},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34075015783309937},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23541584610939026},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23197254538536072},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.13906845450401306},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.11116230487823486},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eiconrus.2017.7910575","doi":"https://doi.org/10.1109/eiconrus.2017.7910575","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eiconrus.2017.7910575","pdf_url":null,"source":{"id":"https://openalex.org/S4306422515","display_name":"IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W177037875","https://openalex.org/W1485855914","https://openalex.org/W1530765221","https://openalex.org/W1557244636","https://openalex.org/W1966136723","https://openalex.org/W2100738443","https://openalex.org/W2113263990","https://openalex.org/W2158487724","https://openalex.org/W2165190641","https://openalex.org/W4301264637"],"related_works":["https://openalex.org/W2052381579","https://openalex.org/W2130514654","https://openalex.org/W2158487724","https://openalex.org/W3010651687","https://openalex.org/W2593932422","https://openalex.org/W79275640","https://openalex.org/W2791675499","https://openalex.org/W1564656499","https://openalex.org/W2114661320","https://openalex.org/W2138858358"],"abstract_inverted_index":{"As":[0],"the":[1,5,8,20,41,52,57,90,94,108,113,120,127,136,141,152,155,161,165,168,173,179,185,190,202,210],"technology":[2],"decreases":[3],"beyond":[4],"28nm":[6],"node,":[7],"area":[9],"of":[10,22,51,67,83,102,112,130,146,154,160,167,172,217],"VLSI":[11],"elements":[12],"and":[13,19,44,76,110,204,219],"supply":[14,37,77],"voltage":[15,33],"level":[16,21],"reduce":[17],"significantly,":[18],"integration":[23],"increases.":[24],"This":[25],"leads":[26],"to":[27,72,106,164,194,207],"new":[28],"effects":[29],"such":[30],"as":[31],"crosstalk,":[32],"drop":[34],"at":[35,135],"power":[36],"rails":[38],"(IR-drop":[39],"effect),":[40],"substrate":[42],"noise":[43],"others.":[45],"The":[46,63,80,100,123,144,158,182],"peak":[47,95,114,142,227],"current":[48,65,96,115,213,228],"becomes":[49],"one":[50],"most":[53],"important":[54],"factors":[55],"affecting":[56],"combinational":[58],"CMOS":[59,68],"circuits":[60],"design":[61],"flow.":[62],"maximum":[64,211],"value":[66,75,97],"IC":[69,212,226],"is":[70,105,149,199,231],"used":[71],"find":[73,208],"IR-drop":[74],"buses":[78],"width.":[79],"existing":[81],"methods":[82],"upper":[84,116],"bound":[85,205,220],"estimate":[86],"do":[87],"not":[88],"provide":[89],"required":[91],"accuracy":[92,109],"for":[93,189],"estimation":[98,229],"problem.":[99],"aim":[101],"this":[103,195],"paper":[104],"improve":[107],"validity":[111],"bounds":[117],"based":[118],"on":[119],"resolution":[121,156],"method.":[122,157],"proposed":[124],"approach":[125],"finds":[126],"maximal":[128],"subset":[129],"gates":[131,191],"that":[132],"can":[133,175],"switch":[134],"same":[137],"time":[138],"thus":[139],"providing":[140],"current.":[143],"hypergraph":[145,162,174,198],"logical":[147],"restrictions":[148],"constructed":[150],"with":[151,222],"help":[153],"vertices":[159,171],"correspond":[163],"outputs":[166,192],"gates.":[169],"Several":[170],"be":[176],"connected":[177],"by":[178,201],"only":[180],"edge.":[181,196],"edge":[183],"determines":[184],"simultaneous":[186],"switching":[187],"prohibition":[188],"belongs":[193],"A":[197,215],"solved":[200],"branch":[203,218],"method":[206,221,230],"out":[209],"consumption.":[214],"comparison":[216],"a":[223],"standard":[224],"worst-case":[225],"made.":[232]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-11-05T12:25:35.769452","created_date":"2017-05-12T00:00:00"}
