{"id":"https://openalex.org/W2594420159","doi":"https://doi.org/10.1109/mwscas.2016.7870032","title":"Self-timed automatic test pattern generation for null convention logic","display_name":"Self-timed automatic test pattern generation for null convention logic","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2594420159","doi":"https://doi.org/10.1109/mwscas.2016.7870032","mag":"2594420159"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2016.7870032","doi":"https://doi.org/10.1109/mwscas.2016.7870032","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7870032","pdf_url":null,"source":{"id":"https://openalex.org/S4210192229","display_name":"IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","issn_l":"1548-3746","issn":["1548-3746","1558-3899"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082672005","display_name":"Nastaran Nemati","orcid":"https://orcid.org/0000-0002-0682-396X","observed_orcids":["https://orcid.org/0000-0002-0682-396X"]},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Nastaran Nemati","raw_affiliation_strings":["University of New South Wales, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of New South Wales, Australia","institution_ids":["https://openalex.org/I31746571"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054563831","display_name":"Mark C. Reed","orcid":"https://orcid.org/0000-0002-8766-324X","observed_orcids":["https://orcid.org/0000-0002-8766-324X"]},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Mark C. Reed","raw_affiliation_strings":["University of New South Wales, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of New South Wales, Australia","institution_ids":["https://openalex.org/I31746571"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030042327","display_name":"Sri Parameswaran","orcid":"https://orcid.org/0000-0003-0435-9080","observed_orcids":["https://orcid.org/0000-0003-0435-9080"]},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Sri Parameswaran","raw_affiliation_strings":["University of New South Wales, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of New South Wales, Australia","institution_ids":["https://openalex.org/I31746571"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057674619","display_name":"Karl M. Fant","orcid":"https://orcid.org/0000-0003-0951-2136","observed_orcids":["https://orcid.org/0000-0003-0951-2136"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Karl Fant","raw_affiliation_strings":["Theseus Logic, California, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Theseus Logic, California, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14988654,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2016","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":9.999999747378752e-05,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"automatic test pattern generation","score":0.9490000009536743},{"id":"https://openalex.org/keywords/null-convention-logic","display_name":"null convention logic","score":0.921999990940094},{"id":"https://openalex.org/keywords/asynchronous-circuits","display_name":"asynchronous circuits","score":0.8389999866485596},{"id":"https://openalex.org/keywords/stuck-at-faults","display_name":"stuck-at faults","score":0.8619999885559082},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"fault coverage","score":0.7639999985694885}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8684012293815613},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7343426942825317},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6930312514305115},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5977968573570251},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.5920632481575012},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5012285709381104},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.46732062101364136},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.44150981307029724},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.438278466463089},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4359491467475891},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4209863543510437},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4203439950942993},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.419960618019104},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3764323890209198},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.33436208963394165},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3186954855918884},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3166067600250244},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13058960437774658},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0933694839477539},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.08738654851913452},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0692664384841919},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/mwscas.2016.7870032","doi":"https://doi.org/10.1109/mwscas.2016.7870032","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7870032","pdf_url":null,"source":{"id":"https://openalex.org/S4210192229","display_name":"IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","issn_l":"1548-3746","issn":["1548-3746","1558-3899"],"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":["jufo-1","norway-1"],"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},{"id":"mag:2745930038","doi":null,"is_oa":false,"landing_page_url":"http://jglobal.jst.go.jp/en/public/201702239926672517","pdf_url":null,"source":{"id":"https://openalex.org/S4306512817","display_name":"IEEE Conference Proceedings","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":"IEEE Conference Proceedings","raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2031240799","https://openalex.org/W2053931020","https://openalex.org/W2081240624","https://openalex.org/W2085028021","https://openalex.org/W2091960397","https://openalex.org/W2102327308","https://openalex.org/W2117939640","https://openalex.org/W2142852319","https://openalex.org/W2148195612","https://openalex.org/W2155694037","https://openalex.org/W2156101882","https://openalex.org/W2159042429","https://openalex.org/W4231670955"],"related_works":["https://openalex.org/W2500757389","https://openalex.org/W2091960397","https://openalex.org/W6889915182","https://openalex.org/W2023686814","https://openalex.org/W1987203435","https://openalex.org/W155990723","https://openalex.org/W2171702487","https://openalex.org/W2181723921","https://openalex.org/W2043949919","https://openalex.org/W1995481531"],"abstract_inverted_index":{"This":[0],"work":[1,52,95],"proposes":[2],"automatic":[3],"test":[4,24,83,118],"pattern":[5],"generation":[6,119],"(ATPG)":[7],"for":[8,57,104,123],"Null":[9],"Convention":[10],"Logic":[11],"(NCL).":[12],"NCL":[13,63,109,126],"is":[14,78,92],"a":[15,33,40],"robust":[16],"asynchronous":[17],"paradigm":[18],"that":[19],"introduces":[20],"new":[21],"challenges":[22],"to":[23,29],"and":[25,36,111],"testability":[26],"algorithms":[27,120],"due":[28],"the":[30,37,86,93],"lack":[31],"of":[32,39,43,50,67,74,88,108],"clock":[34],"signal":[35],"presence":[38],"large":[41],"number":[42],"state":[44],"holding":[45],"elements.":[46],"The":[47,72,116],"main":[48],"features":[49],"this":[51,91],"are":[53,121],"clockless,":[54,99],"self-timed":[55,100],"ATPG":[56,101],"all":[58],"single":[59],"stuck-at":[60],"faults":[61,75,105],"in":[62],"circuits,":[64],"including":[65],"those":[66],"gate":[68],"internal":[69],"feedback":[70],"(GIF).":[71],"detection":[73],"on":[76,106],"GIF":[77,107],"performed":[79],"with":[80,102,112,128],"no":[81,113],"added":[82],"hardware.":[84],"To":[85],"extent":[87],"our":[89],"knowledge,":[90],"first":[94],"which":[96],"has":[97],"addressed":[98],"coverage":[103],"gates":[110],"area":[114],"overhead.":[115],"proposed":[117],"evaluated":[122],"several":[124],"real-size":[125],"circuits":[127],"average":[129],"96.2%":[130],"fault":[131],"coverage.":[132]},"counts_by_year":[],"updated_date":"2026-10-26T11:51:55.731654","created_date":"2017-03-16T00:00:00"}
