{"id":"https://openalex.org/W2564772016","doi":null,"title":"Implementation of 64 Bit KoggeStone Carry Select Adder with BEC for Efficient Area","display_name":"Implementation of 64 Bit KoggeStone Carry Select Adder with BEC for Efficient Area","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W2564772016","mag":"2564772016"},"language":"en","primary_location":{"id":"mag:2564772016","doi":null,"is_oa":false,"landing_page_url":"https://works.bepress.com/article/50/","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042248042","display_name":"B. Tapasvi","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"B. Tapasvi","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067044065","display_name":"K. Bala Sindhuri","orcid":"https://orcid.org/0000-0001-7892-2062","observed_orcids":["https://orcid.org/0000-0001-7892-2062"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K. Bala Sinduri","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034242033","display_name":"I.Chaitanya Varma","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"I.Chaitanya Varma","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5035443202","display_name":"N. Udaya Kumar","orcid":"https://orcid.org/0000-0001-8713-9109","observed_orcids":["https://orcid.org/0000-0001-8713-9109"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"N. Udaya Kumar","raw_affiliation_strings":[],"raw_orcid":"https://orcid.org/0000-0001-8713-9109","affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.466,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.70254674,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":96},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9506999850273132,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9506999850273132,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.0284000001847744,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.005499999970197678,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/64-bit-adder","display_name":"64-bit adder","score":0.9409999847412109},{"id":"https://openalex.org/keywords/bit-error-correction","display_name":"bit error correction","score":0.5820000171661377},{"id":"https://openalex.org/keywords/area-efficient-design","display_name":"area-efficient design","score":0.4580000042915344},{"id":"https://openalex.org/keywords/carry-propagation","display_name":"carry propagation","score":0.4309999942779541},{"id":"https://openalex.org/keywords/digital-arithmetic-circuits","display_name":"digital arithmetic circuits","score":0.41100001335144043}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7107988595962524},{"id":"https://openalex.org/C117011727","wikidata":"https://www.wikidata.org/wiki/Q1278488","display_name":"Bit (key)","level":2,"score":0.6888799667358398},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6855151653289795},{"id":"https://openalex.org/C2776299755","wikidata":"https://www.wikidata.org/wiki/Q432449","display_name":"Carry (investment)","level":2,"score":0.6126935482025146},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5493646264076233},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4274875223636627},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.36650294065475464},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2398492395877838},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2380504310131073},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18811476230621338},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.10704901814460754},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:2564772016","doi":null,"is_oa":false,"landing_page_url":"https://works.bepress.com/article/50/","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1495697738","https://openalex.org/W2601056739","https://openalex.org/W2586951095","https://openalex.org/W7172316278","https://openalex.org/W3025749060","https://openalex.org/W2745374891","https://openalex.org/W6922249178","https://openalex.org/W2513420339","https://openalex.org/W7074686011","https://openalex.org/W6941079764"],"abstract_inverted_index":null,"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-10-12T09:40:04.860316","created_date":"2017-01-06T00:00:00"}