{"id":"https://openalex.org/W2532736396","doi":"https://doi.org/10.1109/iccic.2015.7435657","title":"All digital phase locked loop with input clock fail detector","display_name":"All digital phase locked loop with input clock fail detector","publication_year":2015,"publication_date":"2015-12-01","ids":{"openalex":"https://openalex.org/W2532736396","doi":"https://doi.org/10.1109/iccic.2015.7435657","mag":"2532736396"},"language":"en","primary_location":{"id":"doi:10.1109/iccic.2015.7435657","doi":"https://doi.org/10.1109/iccic.2015.7435657","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccic.2015.7435657","pdf_url":null,"source":{"id":"https://openalex.org/S7407088108","display_name":"IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","raw_type":"proceedings-article"},"volume":null,"type":"conference-paper","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086660220","display_name":"T V Aswathi","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"T V Aswathi","raw_affiliation_strings":["Department of Electronics and Communication, Amrita Vishwa Vidhyapeetham, Bengaluru Campus, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, Amrita Vishwa Vidhyapeetham, Bengaluru Campus, India","institution_ids":["https://openalex.org/I81556334"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087366460","display_name":"P. Sathish Kumar","orcid":"https://orcid.org/0000-0003-1208-1285","observed_orcids":["https://orcid.org/0000-0003-1208-1285"]},"institutions":[{"id":"https://openalex.org/I81556334","display_name":"Amrita Vishwa Vidyapeetham","ror":"https://ror.org/03am10p12","country_code":"IN","type":"education","lineage":["https://openalex.org/I81556334"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"P Sathishkumar","raw_affiliation_strings":["Department of Electronics and Communication, Amrita Vishwa Vidhyapeetham, Bengaluru Campus, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication, Amrita Vishwa Vidhyapeetham, Bengaluru Campus, India","institution_ids":["https://openalex.org/I81556334"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I81556334"],"apc_list":null,"apc_paid":null,"fwci":0.8316,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61031057,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/all-digital-phase-locked-loop","display_name":"all-digital phase-locked loop","score":0.9829999804496765},{"id":"https://openalex.org/keywords/clock-generator","display_name":"clock generator","score":0.6060000061988831},{"id":"https://openalex.org/keywords/system-on-chip","display_name":"system-on-chip","score":0.7789999842643738},{"id":"https://openalex.org/keywords/stuck-at-fault-detection","display_name":"stuck-at fault detection","score":0.7919999957084656},{"id":"https://openalex.org/keywords/digitally-controlled-oscillator","display_name":"digitally controlled oscillator","score":0.7250000238418579},{"id":"https://openalex.org/keywords/verilog-design","display_name":"Verilog design","score":0.5139999985694885}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7301273345947266},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.7290707230567932},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.6706558465957642},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.6124604344367981},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5827444791793823},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5642074942588806},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.558419406414032},{"id":"https://openalex.org/C110086884","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase detector","level":3,"score":0.5458583831787109},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.537590503692627},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.5005612373352051},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.4707242548465729},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.44391703605651855},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.42224031686782837},{"id":"https://openalex.org/C2778426721","wikidata":"https://www.wikidata.org/wiki/Q1225105","display_name":"Digital clock","level":3,"score":0.41825270652770996},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4124056100845337},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4005400538444519},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37659066915512085},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3735244870185852},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.22403007745742798},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.18187415599822998},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16479545831680298},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1533982753753662},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.14006537199020386},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12075582146644592},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06669047474861145}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iccic.2015.7435657","doi":"https://doi.org/10.1109/iccic.2015.7435657","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iccic.2015.7435657","pdf_url":null,"source":{"id":"https://openalex.org/S7407088108","display_name":"IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W60344427","https://openalex.org/W1495597551","https://openalex.org/W1544275318","https://openalex.org/W1599994156","https://openalex.org/W1990548102","https://openalex.org/W1999102886","https://openalex.org/W2045516164","https://openalex.org/W2137120286","https://openalex.org/W2166792641","https://openalex.org/W2549207891","https://openalex.org/W4285719527","https://openalex.org/W6729773611"],"related_works":["https://openalex.org/W2166792641","https://openalex.org/W2169967707","https://openalex.org/W1990548102","https://openalex.org/W1498944944","https://openalex.org/W1978946573","https://openalex.org/W2313934538","https://openalex.org/W7098764390","https://openalex.org/W2223999418","https://openalex.org/W1924784197","https://openalex.org/W2104076434"],"abstract_inverted_index":{"All":[0,52,67],"Digital":[1,53,68],"Phase":[2,54,69],"Locked":[3,55,70],"Loops":[4],"are":[5],"widely":[6],"used":[7,30,89],"as":[8,39],"clock":[9,24,61,105,136,146],"generators":[10,25],"in":[11,73,97,158],"multiprocessor":[12],"system":[13,19],"on":[14],"chips.":[15],"An":[16],"error":[17],"detection":[18,120,142],"is":[20,64,76,88,121,156,166,170],"crucial":[21],"for":[22,90,138,148],"such":[23],"since":[26],"it":[27,129,165],"can":[28],"be":[29],"to":[31,35,40,78,82],"notify":[32],"different":[33],"processors":[34],"shut":[36],"down":[37],"so":[38],"prevent":[41],"the":[42,91,110,117],"propagation":[43],"of":[44,112,150],"a":[45],"faulty":[46],"clock.":[47],"In":[48],"this":[49,74],"work,":[50],"an":[51,58,124],"Loop":[56,71],"with":[57],"improved":[59],"input":[60,104,113],"failure":[62],"detector":[63,107],"presented.":[65],"The":[66,93,103],"proposed":[72],"paper":[75],"designed":[77],"operate":[79],"from":[80],"61KHz":[81],"42Mhz.":[83],"A":[84],"completely":[85],"digital":[86],"approach":[87],"design.":[92],"design":[94,155],"achieves":[95],"lock":[96],"less":[98],"than":[99],"5":[100],"reference":[101,145],"cycles.":[102],"fail":[106],"circuit":[108],"detects":[109],"loss":[111],"signal":[114],"and":[115,127,143,163],"notifies":[116],"controller.":[118],"Fault":[119],"possible":[122],"at":[123,140],"early":[125],"stage":[126],"hence,":[128],"takes":[130],"only":[131],"2":[132],"Digitally":[133],"Controlled":[134],"Oscillator":[135],"cycles":[137],"stuck":[139],"fault":[141,152],"1":[144],"cycle":[147],"out":[149],"limit":[151],"detection.":[153],"Entire":[154],"done":[157,171],"Verilog":[159],"hardware":[160],"description":[161],"language":[162],"hence":[164],"highly":[167],"versatile.":[168],"Synthesis":[169],"using":[172],"cadence":[173],"RTL":[174],"compiler.":[175]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2016-10-28T00:00:00"}
