{"id":"https://openalex.org/W2503555158","doi":"https://doi.org/10.1016/b978-0-12-408082-9.00011-7","title":"Memory Protection Unit (MPU)","display_name":"Memory Protection Unit (MPU)","publication_year":2013,"publication_date":"2013-11-02","ids":{"openalex":"https://openalex.org/W2503555158","doi":"https://doi.org/10.1016/b978-0-12-408082-9.00011-7","mag":"2503555158"},"language":"en","primary_location":{"id":"doi:10.1016/b978-0-12-408082-9.00011-7","doi":"https://doi.org/10.1016/b978-0-12-408082-9.00011-7","is_oa":false,"landing_page_url":"https://doi.org/10.1016/b978-0-12-408082-9.00011-7","pdf_url":null,"source":{"id":"https://openalex.org/S4306463230","display_name":"Elsevier eBooks","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"ebook platform"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Definitive Guide to ARM\u00ae CORTEX\u00ae-M3 and CORTEX\u00ae-M4 Processors","raw_type":"book-chapter"},"parent_works":[{"id":"https://openalex.org/W4236348980","display_name":"The Definitive Guide to ARM\u00ae CORTEX\u00ae-M3 and CORTEX\u00ae-M4 Processors","relationship":"volume"}],"lineage":["https://openalex.org/W2503555158","https://openalex.org/W4236348980"],"child_works_count":0,"type":"book-chapter","is_traditional":true,"indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079733588","display_name":"Joseph Yiu","orcid":null,"observed_orcids":[]},"institutions":[{"id":"https://openalex.org/I2801109035","display_name":"ARM (United Kingdom)","ror":"https://ror.org/04mmhzs81","country_code":"GB","type":"company","lineage":["https://openalex.org/I2801109035"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Joseph Yiu","raw_affiliation_strings":["ARM Ltd., Cambridge, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARM Ltd., Cambridge, UK","institution_ids":["https://openalex.org/I2801109035"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5079733588"],"corresponding_institution_ids":["https://openalex.org/I2801109035"],"apc_list":null,"apc_paid":null,"fwci":0.997,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.69362993,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":88,"max":93},"biblio":{"volume":null,"issue":null,"first_page":"355","last_page":"378"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.638700008392334,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.638700008392334,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.11190000176429749,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.08799999952316284,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memory-protection-unit","display_name":"memory protection unit","score":0.8489999771118164},{"id":"https://openalex.org/keywords/arm-cortex-m3","display_name":"ARM Cortex-M3","score":0.8999999761581421},{"id":"https://openalex.org/keywords/arm-cortex-m4","display_name":"ARM Cortex-M4","score":0.9950000047683716},{"id":"https://openalex.org/keywords/arm-cortex-m0","display_name":"ARM Cortex-M0","score":0.9850000143051147},{"id":"https://openalex.org/keywords/embedded-processors","display_name":"embedded processors","score":0.5690000057220459},{"id":"https://openalex.org/keywords/memory-protection","display_name":"memory protection","score":0.8220000267028809}],"concepts":[{"id":"https://openalex.org/C2778514511","wikidata":"https://www.wikidata.org/wiki/Q1374194","display_name":"Programmer","level":2,"score":0.827315628528595},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5826904773712158},{"id":"https://openalex.org/C26771161","wikidata":"https://www.wikidata.org/wiki/Q16980","display_name":"ARM architecture","level":2,"score":0.4339102506637573},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3778287172317505}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1016/b978-0-12-408082-9.00011-7","doi":"https://doi.org/10.1016/b978-0-12-408082-9.00011-7","is_oa":false,"landing_page_url":"https://doi.org/10.1016/b978-0-12-408082-9.00011-7","pdf_url":null,"source":{"id":"https://openalex.org/S4306463230","display_name":"Elsevier eBooks","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"listed_in":[],"host_organization":"https://openalex.org/P4310320990","host_organization_name":"Elsevier BV","host_organization_lineage":["https://openalex.org/P4310320990"],"host_organization_lineage_names":["Elsevier BV"],"type":"ebook platform"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"The Definitive Guide to ARM\u00ae CORTEX\u00ae-M3 and CORTEX\u00ae-M4 Processors","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1211417354","https://openalex.org/W3026093940","https://openalex.org/W3021355446","https://openalex.org/W4379517519","https://openalex.org/W4289713426","https://openalex.org/W2504221821","https://openalex.org/W2005277718","https://openalex.org/W3020941691","https://openalex.org/W2300737475","https://openalex.org/W69707633"],"abstract_inverted_index":null,"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-11-14T11:04:58.165337","created_date":"2016-08-23T00:00:00"}