{"id":"https://openalex.org/W2486413709","doi":null,"title":"Extended data cache prefetching using a reference prediction table","display_name":"Extended data cache prefetching using a reference prediction table","publication_year":1997,"publication_date":"1997-01-01","ids":{"openalex":"https://openalex.org/W2486413709","mag":"2486413709"},"language":"en","primary_location":{"id":"mag:2486413709","doi":null,"is_oa":false,"landing_page_url":"http://dl.acm.org/citation.cfm?id=997562","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null},"volume":null,"type":"article","is_traditional":true,"indexed_in":[],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029147434","display_name":"Donglok Kim","orcid":null,"observed_orcids":[]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Donglok Kim","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5100616248","display_name":"Yongmin Kim","orcid":"https://orcid.org/0000-0002-8551-8022","observed_orcids":["https://orcid.org/0000-0002-8551-8022"]},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yongmin Kim","raw_affiliation_strings":[],"raw_orcid":null,"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":0,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.0010000000474974513,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.0005000000237487257,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cache-prefetching","display_name":"cache prefetching","score":0.8970000147819519},{"id":"https://openalex.org/keywords/data-cache","display_name":"data cache","score":0.6930000185966492},{"id":"https://openalex.org/keywords/memory-latency","display_name":"memory latency","score":0.6840000152587891}],"concepts":[{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.9879881143569946},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8427102565765381},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7335044145584106},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5565921068191528},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.48009470105171204},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.47429659962654114},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.4441729485988617},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.3197769522666931},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3055552840232849},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0931863784790039},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.07839974761009216}],"mesh":[],"locations_count":1,"locations":[{"id":"mag:2486413709","doi":null,"is_oa":false,"landing_page_url":"http://dl.acm.org/citation.cfm?id=997562","pdf_url":null,"source":null,"license":null,"license_id":null,"version":null,"is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":null}],"best_oa_location":null,"sustainable_development_goals":[],"study_designs":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2128462109","https://openalex.org/W5593215","https://openalex.org/W4245989361","https://openalex.org/W2002956579","https://openalex.org/W7097152851","https://openalex.org/W4394998508","https://openalex.org/W7100399580","https://openalex.org/W7099768612","https://openalex.org/W7098883909","https://openalex.org/W2142780119"],"abstract_inverted_index":{"The":[0,245,275,305],"rapid":[1],"advances":[2],"in":[3,15,20,42,100,150,212,316],"the":[4,16,21,26,30,43,64,70,93,97,101,104,113,125,139,151,158,166,170,184,194,199,216,222,236,255,261,267,272,297,302,314,317,324,329],"VLSI":[5],"technology":[6],"and":[7,83,106,220,300,326],"computer":[8],"architecture":[9],"have":[10,88,128,135,155],"made":[11],"a":[12,129,180,285,293],"significant":[13,181],"improvement":[14,315],"CPU":[17,46,162],"performance":[18,33],"possible":[19],"last":[22],"30":[23],"years.":[24,58],"However,":[25],"growth":[27],"rate":[28],"of":[29,39,45,63,103,132,183,206,287],"memory":[31,53,71,108],"system":[32],"has":[34],"remained":[35],"slower":[36],"than":[37,266],"that":[38,127,157,173,190,313],"microprocessors,":[40],"resulting":[41],"number":[44,131],"clock":[47],"cycles":[48,160,164,197,299],"required":[49],"to":[50,68,91,121,142,227,235,283],"access":[51],"main":[52],"doubling":[54],"approximately":[55],"every":[56],"6.2":[57],"\r\nCache":[59],"prefetching":[60,303],"is":[61,147,174,264,321],"one":[62],"most":[65],"useful":[66],"techniques":[67],"overcome":[69],"latency":[72],"problems.":[73],"Many":[74],"sophisticated":[75],"methods":[76],"such":[77],"as":[78],"SPT":[79],"(Stride":[80],"Prediction":[81,86,240],"Table)":[82,87,241],"RPT":[84,238,252,280],"(Reference":[85,239],"been":[89],"shown":[90],"predict":[92],"prefetch":[94,118,223],"address":[95,228],"using":[96],"stride":[98,263],"(difference":[99],"addresses":[102],"current":[105],"previous":[107],"accesses)":[109],"information":[110],"extracted":[111],"from":[112],"instruction":[114,168],"stream.":[115],"While":[116],"these":[117,229],"mechanisms":[119],"seem":[120],"work":[122],"well":[123],"for":[124,138,323,328],"loops":[126],"large":[130],"iterations":[133],"or":[134],"enough":[136],"time":[137,320],"prefetched":[140,200,207],"data":[141,201,208,242],"become":[143],"available":[144],"before":[145],"it":[146],"actually":[148],"used":[149],"next":[152,256],"iteration,":[153],"we":[154,191,231],"found":[156],"hit-wait":[159,273,298],"(the":[161],"stall":[163],"when":[165,260],"load/store":[167],"hits":[169],"cache":[171,185,195,243,257,268,289,318],"line":[172,258,269,290],"currently":[175],"being":[176],"prefetched)":[177],"can":[178,192,209],"occupy":[179],"portion":[182],"service":[186,196,319],"time.":[187],"This":[188],"means":[189],"reduce":[193],"if":[198],"arrive":[202],"earlier.":[203],"Early":[204],"arrival":[205],"be":[210],"accelerated":[211],"two":[213,233,288],"ways:":[214],"advancing":[215],"perfetch":[217],"issue":[218,284],"timing":[219],"increasing":[221],"throughput.":[224,304],"\r\nIn":[225],"order":[226],"issues,":[230],"present":[232],"extensions":[234],"existing":[237],"prefetching.":[244],"first":[246],"algorithm,":[247,277],"SSE-RPTP":[248,325],"(Small":[249],"Stride":[250],"Extended":[251],"Prefetch),":[253,281],"prefetches":[254,291],"even":[259],"detected":[262],"smaller":[265],"size,":[270],"reducing":[271,296],"cycles.":[274],"second":[276],"XRPTP":[278],"(eXtended":[279],"tries":[282],"maximum":[286],"at":[292],"time,":[294],"further":[295],"improving":[301],"simulation":[306],"results":[307],"on":[308],"11":[309],"SPEC92":[310],"programs":[311],"show":[312],"34.3%":[322],"37.9%":[327],"XRPTP,":[330],"respectively.":[331]},"counts_by_year":[],"updated_date":"2026-10-16T09:59:22.235173","created_date":"2016-08-23T00:00:00"}